MINATEC

In the context of scaling and increased density, research in micro-electronics is facing power consumption control (directly linked with environmental issues). In this context one main objectif of today's research is to decrease circuit power consumption.
Therefore, LETI is involved in 3D circuit integration for future CMOS based circuits. These circuits are a priori thought to increase cicruit density and at the same time decrease power consumption.

In the context of scaling and increased density, research in micro-electronics is facing power consumption control (directly linked with environmental issues). In this context one main objectif of today's research is to decrease circuit power consumption.
Therefore, LETI is involved in 3D circuit integration for future CMOS based circuits. These circuits are a priori thought to increase cicruit density and at the same time decrease power consumption.
Technologically, fabricating upper layers requieres specific low temperature process developments in order to maintain excellent upper layer transistors performance without degrading the initial performance of the lower transistors.
In addition, low temperature process is also interesting to boost the transistor characteristic as it allows to have better controled metal gate and very good gate oxide quality and to decrease dopant diffusion.

The first objectif of the PhD is to fabricate 3D circuits. This relies on the optimization of the low temperature process, especially the doping of source and drain and the epitaxy of raised source and drain. In close collaboration with technological teams, the PhD student will develop these basic steps and will further integrate them in a CMOS process flow. In addition advanced characterization of the transistors will provide quantificatio of the gain with respect to a standard process.
Simulation and conception will be used to evaluate the advantages in term of circuits.

The PhD student is asked to be innovative and to like working in a team.