MINATEC

CEA/LETI presentation :

CEA/LETI presentation :

CEA-LETI, the Laboratory for Electronics & Information Technology has a considerable investment in personnel (staff is approximately 1200 people, among whom 850 CEA employees), know-how and equipment. LETI is one of the largest applied research laboratories in Europe. The main activities of LETI are dealing with electronics, microelectronics, microsystems, and optoelectronics. LETI mainly aims at helping industrial partners to improve their competitiveness through technological innovation in the field of electronics and microelectronics. LETI has also an active patent policy (more than 100 new patents per year). Inside the Circuits and Systems Design (DCIS) Department, the ASIC design team (SCME, Service Conception pour les Microtechnologies Emergentes) is more than 80 people composed of engineers and PhD students. Main activities are related to digital-, RF- , analog- design, devices modelling and characterisation, IC tests, and layout. Low power design is one of the strong activities, covering SOI technology design, power management, low-power architectures.

 Context:

The great success of the microelectronic in the past decades is mainly due to geometrical scaling of IC dimensions, thus bringing down the cost per transistor for every new technology node (Moore’s Law). In the deca-nanometer range, physical parasitic elements lead to scaling limitations which decrease the circuit performance gains for the new generation nodes. Thanks to an excellent electrostatic control of the channel and the low parasitic capacitances, FDSOI technology appears to be an excellent candidate for the future generation of processors in order to preserve the scaling law. Today, one major challenge is to set up Multi-VT device options. In Thin BOX FDSOI technology, an original and simple concept has been recently proposed to fulfil this issue.

 Work description:

The aim of the proposed work is to implement the proposed method in digital circuits. The study will address standard cell layout to co-integrate the Multi-VT devices efficiently (density).  First, the trainee will work at standard cell level (logic gate, filler…).  Second, he will make the physical design of a low power application. The various steps of this study include the following:

• Bibliography on FDSOI and UT2B-FDSOI technologies
• Bibliography on standard cells
• Study how to set up efficiently multi-VT standard cell at layout level
• Physical implementation of a low power application
• International communication

 Profil candidat :

The candidate is in last year of engineer school or master in microelectronics. He must have an experience on designing CMOS digital circuits.

 Location of work : MINATEC – LETI (Grenoble)

Contact name : Olivier THOMAS - 04 38 78 29 54  - olivier.thomas@cea.fr