Context :
Embedded systems are increasingly complex and require more and more computing power. Moreover, they must be adaptable to the quick evolution of applications that can need a very high level of performance. For facing these issues, modern architectures embed more and more processing resources (dedicated and programmable) in order to increase both their computing power and the number of supported application domains.
Thus, one major issue is related to the design techniques that need to be employed for implementing these systems. It becomes now mandatory to develop a high-level simulator to refine the design as far as the gate-level description. The goal of this software prototyping technique is to provide a platform for software developments at the earliest in the design phase, but also to be able to explore the numerous architectural solutions that may be used to answer particular application needs. Thus, only a high-level simulator able to provide the user with sufficiently precise information can permit a correct sizing of the architecture and the choice of solutions leading to the best transistor and energy efficiencies. This architectural exploration phase is done using a model of the architecture which is refined during the design cycle in order to gain precision. This process enables the designer to progressively validate the architectural choices. Thus, during the design phase, the simulators simultaneously embed different levels of description (VHDL, SystemC, etc.) and emulation solutions are used to accelerate the simulation of VHDL source code.
Based on technological evolution, these complex systems will be composed soon by billions of transistors on the same chip, in a context where design time must be as short as possible to lower the time to market. The only solution for these software prototypes is to increase their abstraction level at the expense of their precision. So, even if the resulting platform will be sufficient for software developments, it will be no longer compatible with architectural exploration. This major challenge may have important consequences and solutions must be found to face this issue.
Problem :
During this Ph.D. thesis, the candidate will have to find out solutions related to the system behavior observability as well as its performance analysis. Nowadays, the processing of information, which are acquired during the simulation, is done in software by the computing resources that execute the software prototype. The information, which are needed for the architectural exploration phase, are increasingly difficult to understand and may become more complex to process that the simulated system itself. Information about power consumption, temperature and reliability are for example necessary to consider for the exploration. Additionally, if the execution support is no longer programmable (e.g. on an emulator, for example), all information at the system level are lost. Unfortunately, it would be particularly useful to ensure a continuation during the observation process of the system behavior, whatever is the description level. Finally, along with the increase of system complexity, a huge number of signals or variables need to be observed, and it will be mandatory to pre-process these information before sending them to the user interface. In fact, every communication with this interface leads to important temporal costs.
Work during the Ph.D. Thesis:
This Ph.D. thesis aims at studying and designing hardware/software devices enabling the analysis of performances and the exploration of highly complex systems (e.g. manycore). This observation infrastructure will have to be independent from the chosen description level of the system.
Firstly, this thesis will begin with the study of the State of The Art and will have to identify variables to observe to characterize such systems [1][2]. These variables may be either hardware-related ones (number of cache misses in the memory sub-system, network load, etc.) or software-related ones (code analysis, etc.). This study may take as a basis the results on software prototyping for architectural exploration that were already obtained by the laboratory. Then, the next topic of interest will include information theory and statistical behaviors. Some variables are characterized by a periodic behavior, which can be predictable or invariant during a long period of time, or by the fact that only a sampling of their behavior may be necessary to acquire the most important part of the information. This thesis will have to study these different aspects and to deduce from this study the possible optimizations for the observation of each previously identified variable.
Once the variables have been specified and classified, the thesis will deal with the specification and design of hardware/software devices able to acquire, process and synthesize information. These statistical accelerators will then be able to provide the user with useful and synthetic information, leading to a global and comprehensive view of the state of the system. These observation supports will have to be sufficiently generic and flexible so as to be independent from the observed architecture and to be adapted to different levels of hardware/software description. These supports will have to not be intrusive or to not modify the behavior of the observed system. This observation infrastructure will then be used on a prototyped architecture in order to validate its properties, to measure the provided acceleration and to assess the obtained observation gains. The evaluation of this infrastructure will enable to quantitatively evaluate its interest for the acceleration of the architectural exploration phase of complex systems.
[1] L. Fiorin, G. Palermo, C. Silvano, “MPSoCs Run-Time Monitoring through Networks-on-Chip”, In Proc. of the Design, Automation & Test in Europe Conference & Exhibition (DATE '09), pp.558-561, 20-24 April 2009.
[2] E. Faure, M. Benabdenbi, F. Pêcheux, "Distributed online software monitoring of manycore architectures," In Proc. of the On-Line Testing Symposium (IOLTS'10), pp.56-61, 5-7 July 2010.
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