Electrical characterization of trap-rich layers applied to RF substrate performances
Published : 13 December 2016
The goal of this thesis is to study trap-rich layers embedded in SOI-RF substrates. Material properties (morphology, electrical properties, trapping effects) will be linked with RF performances.
First, the work will be focused on the determination of the traps features. Specific techniques such as Thermally Stimulated Current (TSC) or Current-Deep Level Transient Spectroscopy (I-DLTS) will be developed to achieve this task.
Results of the electrical characterization will be compared with physical properties supplied from data bases for a set of technological variants.
In the same time, different ways to perform samples will be investigated to adapt the structures to the measurements.
Results of the electrical characterization of the trap-rich layers will be compared with RF performances of the SOI substrates. Soitec will provide results from RF measurements and the physical model developed by Soitec will be enhanced.