Strategy of crosspoint non-volatile memory integration in cache hierarchy of a multicore architecture
Published : 24 April 2017
Non volatile memory presents a real opportunity to improve caches performance in a multicore architecture. The goal of this PhD thesis is to propose an innovative approach to integrate and handle this kind of memory in cache’s hierarchy to improve both performance and energy efficiency of computing multicore circuits.
As the bandwidth to external memory increases slower than computational power of multicore processors, the size of embedded memory caches keeps growing. In present circuits, caches can take up to 75 percent of silicon area. Moreover, the last level cache, which is the bigger, has a low access rate and so has a high static power consumption. We can solve both problems thanks to non volatile memories (NVM) because they have a null static power consumption and provide a higher storage density than SRAM memory usually found in caches. More recently, the emergence of crosspoint NVM promises to deliver even higher storage densities.
This PhD thesis aims at exploring new system-level and microarchitectural-level strategies of crosspoint NVM integration in the cache hierarchy of an existing multicore. This kind of memory has a high write cost which must be taken into account while optimizing performance, power and endurance of the circuit. The student will provide a RTL model of a cache integrating crosspoint NVM in an innovative manner.
So, the student must be knowledgeable in processor architectures, RTL design and verification, and have minimal knowledge in low level software (C, operating system). The work will consist firstly in a bibliography of existing proposals to embed NVM in caches, then a research of specific constraints of crosspoint NVM, a proposal of innovative ideas to answer these problematics, an implementation of these ideas and an evaluation. The thesis will end by the writing of a manuscript and the PhD defense.