SystemC Acceleration for multi-physics co-simulation and heterogeneous model complexity
Published : 4 January 2017
The increase in System-on-Chip (SoC) complexity, driven by the reduction in transistor size, called for a design flow integrating validation as early as possible in the design phases. The SystemC hardware description language, is widespread to model and simulate SoCs in this flow. It provides Virtual Prototypes (VP) that ease the development and validation of hardware/software integration in the earliest design phases.
The advent of Internet of Things (IoT) and more generally of autonomous systems requires simulation solution integrating at the same time processing elements but also external actioners and sensors. This calls for SystemC co-simulation with Multiphysics tools. As simulation speed is key to reduce design time and time to market, fast simulation solutions are needed.
CEA and Verimag have both developed state-of-the-art solutions for the acceleration of SystemC simulation. These approaches provide significant acceleration (more than one order of magnitude) to parallel models whose computing complexity is homogeneous. However, they fail to provide significant acceleration when heterogeneous model complexity is encountered. Such heterogeneity historically stemmed from various abstraction levels (CABA, TLM). But Multiphysics simulation will also exhibit strong variation in complexity due to the diversity of physical phenomena.
This thesis will target the definition of a novel parallel SystemC simulation kernel able to accelerate simulations in the context of Multiphysics co-simulation and heterogeneous complexity. To achieve this, the student will leverage the joint usage of state-of-art solutions. The work will take into account models’ synchronization frequencies so as to maximize their parallelism. The thesis will also target the identification of relevant hardware execution support for every SystemC model types, and use this knowledge to define adaptive scheduling of SystemC threads on heterogeneous computing architecture (CPU/GPU/FPGA).