One-day Tutorial INFOS 2011 (Grenoble, France)
21 June 2011
New challenges in Nanoelectronics
Organizer: G. Ghibaudo, IMEP-LAHC (Grenoble)
High mobility channels for advanced CMOS, A. Dimoulas (NCSR, demokritos, Athens, Greece)
Physical trends of high-k oxides: Report from a tour in the Periodic System, O. Engstrom (Poland)
Recent trends in CMOS front-end reliability, B. Kaczer (IMEC, Leuven, B)
Silicon Non Volatile Memories: Paths of Innovation, B. DeSalvo (LETI-CEA, Grenoble)
Nano Characterization of Materials, D. Schroeder (Arizona State Univ. USA)
Advanced modelling and simulations approaches, G. Baccarani (Bologna University, Italy)
High mobility channels for advanced CMOS, A. Dimoulas (NCSR, demokritos, Athens, Greece)
Channel materials like Ge and InGaAs have high mobility and low energy gap so that they can deliver high performance at low power supply voltage in scaled nanoelectronic integrated circuits. Materials, devices and integration challenges for advanced CMOS will be reviewed and potential solutions will be discussed. In the first part of the presentation the focus will be on Ge MOS addressing issues associated with the surface and interface quality, the passivation layer, the gate dielectric and the source and drain regions. Device performance will be discussed in light of recent progress in Ge nMOSFETs and the prospects for an all- Ge CMOS technology. In the second part of the presentation, alternative implementations will be presented such as dual channel CMOS comprising Ge (SiGe) pFETs and III-V nFETs. Device architecture options like inversion type MOS or unconventional quantum well MOS-HEMTs will be critically discussed in terms of materials, performance characteristics and scalability down to the 20 nm critical dimensions. Finally, in the last part of the talk, (co)integration issues on bulk Si or SOI/GeOI substrates will be reviewed
Dr. Dimoulas obtained his Ph.D in Applied Physics from the University of Crete and the Foundation for Research & Technology-Hellas (FORTH) in Greece in 1991 on the characterization of thermal strain in MBE heteroepitaxial III-V semiconductors on Si. He was Human Capital & Mobility Fellow of the EU at the University of Groningen in Holland, Research Fellow at the California Institute of Technology (CALTECH), Pasadena USA, and Research Associate at the University of Maryland at College Park (UMCP) USA. In addition, Dr. Dimoulas was visiting research scientist at IBM Zurich Research Laboratory, Switzerland, in 2006 and 2007. He has coordinated a number of EU-funded ICT/nanoelectronics projects, he has organized INFOS 2007, a number of MRS and E-MRS symposia, and he has been the TPC chair of ESSDERC 2009 in Athens. At present he serves as a member of Process Technology subcommittee of IEDM and the TPC committee of ESSDERC and he is also member of the steering or international advisory committees of ESSDERC-ESSCIRC, ICSI, and INFOS. He has co-authored 110 technical publications including 3 monographs in Springer book chapters; he has given 35 invited and keynote presentations in conferences and summer schools and he has co-edited one Springer book and several special issues/volumes in Journals. He is now Research Director at NCSR DEMOKRITOS in Greece, head of the MBE and Surface Analysis Laboratory, working on high-k dielectrics and high mobility (Ge and III-V) channel materials for advanced CMOS.
Gate oxides for MOSFETs are expected to give galvanic insulation between the transistor gate and the channel while offering a high permittivity for the displacement of charge. As the ultimate leakage mechanism is tunneling, two basic materials properties are critical for fulfilling this task: the dielectric constant and the energy offset values between the energy bands in the oxide and those in the semiconductor. In practice, additional properties exist which may limit the exploitation of such characteristics. The chemical reactivity between the oxide and the silicon crystal, the thermal stability of the oxide, its propensity to include charge carrier traps and interface states and its sensitivity to humidity are examples. Among oxides based on transition and rare earth metals, constrictions of this kind limit the number of possible candidates for the increased demands on future dielectrics. However, while the basic properties of binary oxides are given by Nature, the mixing of oxides to create ternary compounds gives possibilities for engineering. The properties of such materials may in some cases be a median between the properties of the binary oxides building up the compound. In other cases, completely different dielectric qualities occur, for example due to a change in atomic structure of the new material. Can such transformations be predicted from the chemical properties of the elements building up the oxides?
This lecture will discourse the fundamental prerequisites on high-k oxides for CMOS technology at the end of the Roadmap, review their physical and electrical properties and discuss tendencies related to their constituents.
Olof Engström, received a PhD degree in Solid State Physics from the University of Lund in 1975 and was later employed by ASEA AB for research on high power thyristors, by AB Rifa for development of MOS technology and by the Swedish Defence Research Institute for sensor research. In 1984, he came to Chalmers University of Technology as a professor in Solid State Electronics. Between 1996 and 1999, he served as Dean of Chalmers School of Electrical and Computer Engineering and 1999 - 2002 he was the Director of the Microtechnology Center at Chalmers (MC2). From 2003 he is back in research as a professor at the Department of Microtechnology and Nanoscience of MC2. His present research interest is in semiconductor quantum structures and interfaces. In 1991, he founded Samba Sensors
AB, a company for production of fiberoptical pressure sensors.
Recent trends in CMOS front-end reliability, by B. Kaczer (IMEC, Leuven, B)
In order to maintain the trend of ever-increasing performance, several directions have been pursued by the semiconductor industry in the past decade. i) Conventional Si and SiO2 are being replaced by more exotic materials, from high-k gate dielectrics to metal gates and to high-mobility substrates, ii) new (3D) device architectures are being developed, iii) devices are downscaled toward atomic dimensions, while iv) supply voltages are not correspondingly reduced.
All of these developments constitute new challenges for reliability testing and assurance. New characterization techniques have to be developed and degradation mechanisms have to be re-examined in the new materials and devices. In deeply scaled devices, statistical treatment, once confined to the breakdown of thin gate oxides, must be applied to all mechanisms. Finally, when technological solutions start to be inadequate, reliability margin can be increased by considering the particular function of each device in the circuit.
Ben Kaczer is a Senior Reliability Scientist at IMEC, Belgium. He received the M. S. degree in Physical Electronics from Charles University, Prague, Czech Republic, in 1992 and the M. S. and Ph. D. degrees in Physics from The Ohio State University, Columbus, in 1996 and 1998, respectively. For his Ph. D. research on the ballistic-electron emission microscopy of SiO2 and SiC films he received the OSU Presidential Fellowship and support from Texas Instruments, Inc. In 1998 he joined the reliability group of IMEC, Leuven, Belgium where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate FETs, circuits, and characterization of Ge/III-V and MIM devices. He has authored or co-authored more than 200 journal and conference papers, presented invited papers and tutorials at several international conferences, and received 4 Best or Outstanding Paper Awards at IRPS and a Best Paper Award at IPFA. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM conferences.
Silicon Non Volatile Memories: Paths of Innovation by B. DeSalvo (CEA-LETI, Grenoble)
In this presentation, we will make a general overview of the innovative memory solutions and corresponding technological approaches currently studied worldwide in order to meet the requirements of the Tera-bit era, A particular attention will be given to the technical progress obtained during recent years in the emerging semiconductor memory technologies. Several topics will be covered from short-term to long-term memory solutions. In particular, we will discuss ultra-scaled floating gate and charge-trap non-volatile memories for embedded or stand-alone applications, resistive memory technologies (as Phase-Change memories, Magnetic RAM and OXide–based resistive memories), as well as three-dimensional integration approaches, to increase memory density. Finally, also innovative ideas covering thin-film memories, molecular memories and new revolutionary architectures will be presented.”
Barbara De Salvo received the B.S. and M.S. in electronics engineering from the University of Parma, Italy and the Ph.D. degree in microelectronics from the Polytechnics Institute of Grenoble, France. She joined LETI (Laboratory of Electronics and Information Technologies of CEA, Grenoble, France) as a scientist in 1999. She currently manages the “Advanced Memory Technologies Laboratory” in LETI, covering several R&D projects funded by industrial partnerships and French/European institutions. She is author or co-author of more than 200 articles in International Refereed Journals and Conferences, several book chapters and one monography on Silicon Non Volatile Memories edited by John Wiley & Sons. She has supervised several Master and PhD students.
Many semiconductor characterization techniques developed over the years have been adapted to shrinking device dimensions, e.g., scanning tunneling (STM), atomic force (AFM), and transmission electron microscopy (TEM) with sub-nm resolution measurements. After a brief discussion of resolution limits of the major characterization techniques, I will give some examples of methods suitable for the small geometries of nano devices. These include STM, AFM, atomic resolution TEM. Magnetic exchange force microscopy gives atomic resolution combined with spin sensitivity. Probe techniques allow not only atomic resolution measurements, but also precise placement of individual atoms. In off-axis electron beam holography, highly coherent electron beams generate a hologram from which the sample potential is extracted, e.g., the potential distribution in a MOSFET. In X-ray and electron beam tomography a series of projection images form a 3-D reconstruction of an object. A recent implementation, with X-rays achieves 60 nm diffraction-limited spatial resolution. Secondary ion mass spectrometry characterization has also improved with 50 nm resolution possible. The atom probe field ion microscope, a combination of a field ion microscope and a time-of-flight mass spectrometer has single ion sensitivity. A high electric field “evaporates” surface atoms of the specimen and only one atom at a time leaves the specimen generating a picture of atomic distributions. These “physical” characterization techniques will be complemented with electrical characterization methods. Electrical measurements, e.g., current-voltage, capacitance-voltage, are, in principle, similar to those on macro devices. However, due to the small size of nano devices, contacting is a problem and small-diameter STM or AFM probes can be used. Furthermore, surface effects become more important. For example, surface-induced space-charge regions due to Fermi level pinning can deplete a nano wire completely leading to very high resistances making measurements fifficult. Scanning Kelvin probes are used to determine surface potentials. All of these will be discussed.
Dieter K. Schroder has worked with semiconductor material and device electrical characterization for the last 40 years. He received his education at McGill University and at the University of Illinois. He joined the Westinghouse Research Labs. in 1968 where he was engaged in research on various aspects of semiconductor devices, including MOS devices, imaging arrays, power devices, and magnetostatic waves. He spent a year at the Institute of Applied Solid State Physics in Germany during 1978. In 1981 he joined Arizona State University. His current interests are semiconductor devices, defects in semiconductors, semiconductor material and device characterization, low power electronics, photovoltaics and device modeling. He has written two books Advanced MOS Devices and Semiconductor Material and Device Characterization, edited 11 books, has written over 180 papers and 10 book chapters, holds 5 patents, has supervised 104 graduate students, has taught many short courses in the area of Semiconductor Characterization and is an IEEE Life Fellow.
In this tutorial, a wide range of modeling techniques of nanoscale electron devices will be reviewed. The emphasis will be mainly on silicon nanowires, where the carrier transport is confined both structurally and by the gate field, and occurs predominantly in one dimension. At the lower level of the hierarchy, the quantum drift-diffusion (QDD) model resulting from Bohm’s theory of the quantum potential, and its simplified version, namely, the density-gradient (DG) model, will be reviewed. Next, we consider the Boltzmann transport equation (BTE) associated with quantum confinement and its deterministic as well as statistical (Monte Carlo) solution techniques. We then address the quantum transport model, i.e. the open-boundary Schrödinger equation and its solution methodologies, including the quantum-transmitting boundary method (QTBM) and the non-equilibrium Green’s function (NEGF) formalisms. The density functional theory (DFT) based on the Hohenberg-Kohn theorem will be finally illustrated for the calculation of the nanowire band structure.
Giorgio Baccarani (GB) received his Dr. Ing. degree in Electrical Engineering in 1967 and his Dr. degree in Physics in 1969 from the University of Bologna, Italy, where he is now professor of Digital Electronics. He is currently Director of the Research Center on Electronic Systems (ARCES). GB has devoted his research work to various aspects of Microelectronics, including processing technology, device physics and characterization, current transport in semiconductor materials and devices, sub-micron MOSFET optimization and design, numerical analysis of semiconductor devices. His current interests include quantum transport in multigate and nanowire FETs, and transport properties of carbon nanotube and graphene nanoribbon FETs. He has authored or coauthored about 250 papers, and his activity has generated extensive collaborations with national and European Industries, and with research Institutions in Italy and abroad. He is a Fellow of the IEEE and a recipient of the medal of honor from the President of the Republic of Italy “for contributions to the science, culture and art”.