Nocs 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
Nocs - Async 2010 Grenoble
Call for paper
Technical Scope
NOCS is the premier event dedicated to interdisciplinary research on on-chip communication
technology, architecture, design methods and applications, bringing together scientists and
engineers working on NoC innovations from inter-related research communities, including
computer architecture, networking, circuits and systems, embedded systems, and design
automation.
Original papers describing new and previously unpublished results are solicited on all aspects of
NoC technology. Topics of interest include:
• NoC architecture (topology, routing,
arbitration...)
• Novel interconnect links/switches/routers
• Signaling and circuit design for NoC links
• Power and energy issues
• Timing, synchronous/asynchronous
communication
• NoC reliability issues
• NoC services (quality of service, security…)
• Methodologies, tools, design flows and
development environments for NoCs
• Modeling, simulation, and synthesis of NoCs
• Verification, debug & test of NoCs
• Floorplan-aware NoC architecture
optimization
• Physical design of interconnect and NoCs
• 3D stacked, optical & RF on-chip/inpackage
interconnects
• Emerging technologies for NoCs (CNFET,
Nanowires)
• O/S and programming model support for
NoCs
• Mapping of applications onto NoCs
• NoC support for CMP and MPSoCs
• NoCs for FPGAs and structured ASICs
• IP protocol support (AXI, OCP…) and
interoperability support
• Metrics and benchmarks for NoCs
• Multi/many-core workload
characterization & evaluation
• NoC design case studies
Electronic paper submission requires a full paper, up to 10 double-column IEEE format pages,
including figures and references. Papers will be evaluated by the program committee in a blind
review process based on scientific merit, innovation, relevance, and presentation. Proposals for
tutorials, special sessions, and panels are also invited.
A special section related to the theme of the conference will be organized in collaboration with the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Important Dates
• Abstract registration deadline December 11, 2009 (hard deadline)
• Full paper submission deadline December 18, 2009 (hard deadline)
• Proposals for tutorials, special sessions, and panels December 18, 2009
• Notification of acceptance February 12, 2010
• Final version due March 12, 2010
• Symposium May 3-6, 2010