This year, every day of the conference, there will be a poster session to discuss the papers presented on that day. There will three poster sessions, one per day at the end of the afternoon. This is an additional opportunity to present author’s work and creates face to face technical exchanges in a more interactive and relaxed manner.
All authors are therefore expected to bring a poster presenting their work. The format of the poster is usual (A0 or B0). The boards and pins will be provided. The authors should install their poster during the afternoon coffee break, to be ready for the evening poster session.
For our common ASYNC-NOCS 2010 conference, we are pleased to present you this year a complete series of exiting demonstrations. Various demonstrations coming from both academics and industrial partners will present working circuits, working demonstration boards, and up-to-date CAD tools. This is a unique opportunity to see the recent results in the domain of both asynchronous design and Network-on-Chip technologies.
The demonstration session will occur on Wednesday 17:00 – 18:30, in the same place as the poster session.
If conference participants would still like to do some demonstration proposals, this is still possible. Please answer to our Call-for-Demonstration (pdf)
Please find below a summary of the presented demonstrations:
The CHAINworks NoC synthesis flow, Silistix
Demonstration of large speed improvement on contactless banking transactions based on asynchronous hardware, Tiempo
Analysis, synthesis and verification of asynchronous systems using Workcraft, Newcastle University
Magali, a Reconfigurable Digital Baseband for 4G Telecom Applications based on an Asynchronous NoC, CEA-LETI
Synthesis of Self-timed Circuits from Simulink Specifications, Politecnico di Torino
Teak - a synthesiser for the Balsa language, The University of Manchester
Utopium: A superscalar wagged 8051, The University of Manchester
Integration of NoC architectures in the Space Codesign platform, Ecole Polytechnique of Montreal
See details of the Demonstration Session in the program below.
John Bainbridge (email@example.com).
CAD tool demonstration of Silistix tool flow, to generate asynchronous NoC, starting with input specification, through synthesis to simulation.
For more information, see http://www.silistix.com
The demo will show a guided tour through use of the CHAINworks NoC synthesis suite including:
Typically multiple iterations of the above steps are performed to result in the preferred tradeoff of area, power and performance. The networks created support a range of advanced capabilities including clock and power shutoff management and mixed-timing operation, including support for truly asynchronous QDI communication.
Alban d'Halluin (firstname.lastname@example.org)
Director Product Marketing Tiempo.
Tiempo will demonstrate based on an asynchronous 16-bit microcontroller chip and an asynchronous DES chip how a Mastercard PayPass Magstripe transaction (contactless banking transaction) can be accelerated by a factor 8 in processing time.
Ivan Poliakov (email@example.com),
Andrey Mokhov (firstname.lastname@example.org)
Alex Yakovlev (email@example.com)
CAD tools for asynchronous design
A large number of models that are employed in the field of concurrent systems design, such as Petri Nets, Signal Transition Graphs, gate-level circuits, Static Data Flow Structures and Conditional Partial Order Graphs have a common underlying graph structure. Their semantics, however, is defined using additional entities, e.g. tokens or node/arc states, which in turn form the overall state of the system. We jointly refer to such formalisms as Interpreted Graph Models, or IGMs. The similarities in notation allow for links between different IGMs to be created in a way that is very clear for the designer, such as interfaces between formalisms or conversion from one model type into another. This greatly extends the range of applicable analysis techniques. The demonstration presents the current version of Workcraft – a tool designed to provide a flexible common framework for development and application of Interpreted Graph Models. The following use cases are going to be demonstrated:
• Graphical input, simulation and verification of Petri Nets, Signal Transition Graphs, Gate-level circuits, Conditional Partial Order Graphs, and Static Data Flow Structures.
• The design of an asynchronous processor based on Conditional Partial Order Graphs.
• The design of a multi-resource asynchronous arbiter.
• Optimisation of handshake circuits implementation using STG resynthesis.
• Timing and power analysis based on annotated Petri Net simulation.
Romain Lemaire (firstname.lastname@example.org),
Yvain Thonnart (email@example.com),
CEA, LETI, MINATEC, Grenoble, France.
Asynchronous NoC based circuit in 65nm running Telecom Application
MAGALI is a digital baseband chip designed at CEA-LETI based on an asynchronous Network-on-Chip targeting 4G Telecom applications. Thanks to innovative mechanisms, the chip succeeds in mixing high-computation performance (37.3GOPS) and limited power consumption (477mW @ 1.2V). Moreover, fast reconfiguration is handled by distributed micro-programmed controllers.
The aim of the demonstration is to present the MAGALI chip and its integration in a prototyping board. The mapping of a 3GPP-LTE MIMO 4´2 receiver on MAGALI processing cores and corresponding data flows communication on the NoC will be detailed. Then applicative scenarios, including different configuration modes, will be executed on the board and illustrated by relevant signals instrumentation.
Maurizio Tranchero, (firstname.lastname@example.org)
Leonardo M. Reyneri, (email@example.com)
CAD, ESL design for Asynchronous design
This demonstration shows an approach to automatically synthesize Simulink diagrams into asynchronous circuits. This approach is based on the CodeSimulink co-design environment, a tool developed at Politecnico di Torino that previously was able to convert Simulink diagrams into synchronous implementations. Such environment has been extended in two different ways in order to integrate it with conventional FPGA and ASIC flows.
The system generated with FPGAs as target is based on bundle-data implementation, which needs special care during both synthesis and placement in order to maintain circuit correctness. Simulink diagrams are compiled into standard VHDL and synthesized with conventional tools provided by chip manufacturers. The obtained code is constrained to avoid unwanted synthesis optimizations and constrained to implement the "equipotential region" necessary to synthesize the correct number of stages necessary to match delays of combinational logic.
Andrew Bardsley (firstname.lastname@example.org)
School of Computer Science, The university of Manchester
CAD, ESL design for Asynchronous design
Teak is a new synthesiser for the Balsa language. Teak generates networks of macromodular components from Balsa descriptions, like the Balsa System, but uses a different, more conventional set of components instead of Handshake Components.
Synthesis is initially syntax-directed but with a variety of optimizations applied to the resulting networks. The regularity of the chosen component set, and the elasticity of the networks, allows network optimisation to be more successfully applied than with Balsa Handshake Circuits.
Generated networks are elastic compositions of components connected only with push handshake channels and without reliance on the `enclosure' of handshakes between channels. For example, there is no Sequence component, control is carried either with data or by using zero-bit (req/ack) channel pairs to start/indicate completion of operations.
Components are generated from a small number of templates and are very similar to those used by other micropipelined design styles. This is done with the hope that Teak could be used to target into a wider variety of faster circuit and handshaking styles than has previously been possible using Handshake Circuits.
The Teak System consists of:
- A synthesiser from Balsa to Teak component networks
- A mechanism to plot those networks
- A language-level simulator for Balsa
- A programmable peephole optimiser for component networks
- A GUI to drive and visualise optimisation choices
- A prototype `back end' to generate Verilog gate-level implementations of Teak components
In this demonstration I will show the synthesis, optimisation, gate-level netlist generation and simulation of a number of small examples. I will also show a more substantial example: the nanoSpa ARM microprocessor description previously used to illustrate pipelined extensions to/replacements for the Balsa System.
Dr. Charlie Brej, (email@example.com),
School of Computer Science, The University of Manchester.
Utopium is a microprocessor created to demonstrate the wagging technique's ability to extract parallelism from sequential designs and create manufacturing fault tolerant designs.
Wagging creates a parallel design that has a set of bottleneck components duplicated (multiple times if necessary) to yield a faster implementation. These parallel elements are connected in such a way that an early evaluating operation will trigger the next parallel operation to start before the previous one has completed. The level to witch the design is wagged (number of replicated design slices) is completely transparent to the designer. The interfaces and functional behaviour of the design do not change.
The Utopium is a level eleven wagged design, which allows up to eleven parallel operations. In simulations, running general code, the design does not benefit form more than seven slices (due to the lack of a branch predictor), but to explore the saturation point, a higher level was chosen. The design also incorporates a set of small parallel caches which allow the performance to not be impeded by the memory access times.
The slices of the design can be disabled at reset time. This not only allows the level of wagging to be varied, but also any faulty slices to be bypassed. The slice does not necessarily have to be faulty, but may simply contain a slow component and bypassing it may improve preference.
The processor is manufactured in 130nm technology using 250,000 gates.
The demo will present the processor allowing participants to examine it running a variety of benchmarks and varying the level of wagging.
ESL tools for NOC space exploration on the ROC architecture.
Hubert Guerard, (firstname.lastname@example.org), Master student Ecole Polytechnique de Montreal,
Guy Bois, (email@example.com), Professor Ecole Polytechnique de Montreal, and Cofounder of Space Codesign Systems Inc.
This demonstration discusses about the integration of a Network on Chip (NoC) architecture as communication component of a virtual platform. A significant challenge with future highly parallel SoC architectures is to avoid communications being their system bottleneck. NoCs have been proposed as a means to address these issues. In this context, we have developed the Rotator on Chip (nicknamed RoC), a parameterized and scalable NoC architecture based on the token ring concept. This architecture is generic with respect to the number of nodes and data channels. The RoC has been designed to produce a low latency and to maximize the use of the available bandwidth without consuming too much resource. Also, one of the key elements of the electronic system level (ESL) methodology is the concept of platformbased design and more specifically, the use of virtual platforms is the key of simplified and intelligent system designs, embedded systems and systems-on-chips. The Space CodesignTM virtual platform  offers an innovative design environment that allows co-simulation and non-intrusive co-monitoring of specifications, effortless platform exploration for hardware/software partitioning and an automated co-synthesis phase for FPGA or ASIC implementations.
Therefore, based on the RoC architecture, the 3 following steps of our ESL refinement methodology will be presented: 1) simulation and monitoring of the UTF (Untimed Functional Model), 2) mapping, simulation and monitoring of the UTF model on a cycle accurate model of the RoC and 3) replacement of all platform models of RoC, adapters, processors, memories and peripherals by existing RTL IP blocks. The MJPEG application will be used to illustrate concrete features of these 3 steps.
 Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., Paulin, P, «RoC: A Scalable Network on Chip Based on the Token Ring Concept», Proc. of Northeast Workshop on Circuits and Systems, Gatineau, Canada, June 2006.