NOCS 2010

Nocs 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
Nocs - Async 2010 Grenoble

The 4th ACM/IEEE International Symposium on Networks-on-Chip - Grenoble, France, May 3-6, 2010


Complete ASYNC 2010 - NOCS 2010 program


Download the complete program in pdf format




 

Monday, May 3, 2010, Tutorials

For our common ASYNC-NOCS 2010 tutorials, we are pleased to present this year 3 full tracks with full-day and half-day tutorials. The program contains 2 tutorials covering NoC topics, and 3 tutorials covering Async topics.

Most of the tutorials will include both theoretical aspects and some challenging practical work. The participants will have the exciting opportunity to do some real lab exercises on computers, using participant’s laptops or desktop computers.

The tutorials will take place in the laboratories of the CIME facilities (Centre Interuniversitaire de MicroElectronique et Nanotechnologies), see www.cime.inpg.fr, which is located just nearby the MINATEC building.

 

Tutorial N1   9:00 – 12:30

Tutorial N2   9:00 – 12:30

Tutorial A2   9:00 – 12:30

 

Virtual Prototyping of 
NoC-based MPSoC:
Fundamentals & Case Studies
[Slides]

(Part I)

Alain Greiner (UPMC/LIP6),

Nicolas Pouillon (UPMC/LIP6),

Frédéric Pétrot (INPG/TIMA),

Fabien Colas-Bigey (Thales),

Laurent Maillet-Contoz (STMicro),

Nguyen Huy-Nam (Bull).

 

 

Dynamic Power Management of Multi-Core Systems Under Workload- and Technology-driven Variations [Slides]

 

Radu Marculescu (Carnegie Mellon Univ)

Umit Y. Ogras (Intel Corp).

 

 

 

A Simulation Tool for the Study of Metastability in SoCs [Slides]

 

 

Tom Chaney (Blendics LLC),

Dave Zar (Univ. Washington).

 

Room: CIME

Room Minatec, 222+223+224

Room : CIME

                                                                    Lunch, 12:30 – 14:00                

Tutorial N1   14:00 – 17:30

Tutorial A1   14:00 – 17:30

Tutorial A3   14:00 – 17:30

 

Virtual Prototyping of 
NoC-based MPSoC:

Fundamentals & Case Studies [Slides]

 

(Part II)

 

ASIPIDE: a graphical framework to design and debug GALS systems through simulation and prototyping [Slides]

 

Lilian Janin (Univ. Manchester),

Shoujie Li (Univ. Manchester),

Doug Edwards (U. Manchester).

 

 

AHMOSE: Asynchronous High-speed Modeling and Optimization Tool-set [Slides]

 

Eslam Yahya (INPG/TIMA),

Jeremie Hamon(INPG/TIMA),

Laurent Fesquet (INPG/TIMA).

Room: CIME

Room : CIME

Room : CIME

 

  • During the tutorials, there will morning (10:30-11:00) and afternoon (15:30-16:00) coffee breaks. All coffee breaks will take place in the MINATEC Grand Salon.

 

Monday, May 3, 2010, Welcome Reception

19:00 – 22:00

 

ASYNC 2010 – NOCS 2010 - Welcome Reception

 

Room : MINATEC Grand Salon

 

Tuesday, May 4, 2010 (Morning)

 

9:00 – 9:30, Auditorium

ASYNC 2010 - NOCS 2010

Opening Session [Slides]

9:30 – 10:30, Auditorium

1st Keynote

Low-power Bioelectronics for Massively Parallel Neuromonitoring [Slides]

                                                     Pr. Mohamad Sawan, University of Montreal        

Session Chair : Rajit Manohar, Cornell Univ.

10:30 – 11:00, Coffee Break

11:00 – 12:30, Small Hall                              ASYNC        

11:00 – 12:30, Auditorium                            NOCS

Session A1 : Logic and Physical Synthesis

Chair : Steven Nowick, Columbia University

11:00-11:30

Click Elements, An Implementation Style for Data-driven Compilation [Slides]

Ad Peeters1, Frank te Beest1, Mark de Wit1 and Willem Mallon2

1Philips, 2NXP

11:30-12:00

M-of-N Code Decomposition for Indicating Combinational Logic [Slides]

William Toms, Doug Edwards

University of Manchester

12:00-12:30

Concurrency Reduction of Untimed Latch Protocols - Theory and Practice [Slides]

Santosh Varanasi1, Kenneth Stevens1 and Graham Birtwistle2

1University of Utah, 2University of Sheffield

 

 

Session N1 : Flow Control and Routing

Chair: Yvain Thonnart, CEA LETI

11:00-11:30

Evaluating Bufferless Flow-Control for On-Chip Networks [Slides]

George Michelogiannakis and Daniel Sanchez

Stanford University

11:30-12:00

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-Chip Networks [Slides]

Andreas Lankes1,  Thomas Wild1,  Soeren Sonntag2,  Helmut Reinig3,  Andreas Herkersdorf1

1Technische Universität München, 2Lantiq Deutschland GmbH, 3Infineon Technologies AG

12:00-12:30

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing [Slides]

Samuel Rodrigo1,  José Flich1,  Antonio Roca1,  Simone Medardoni2,  Davide Bertozzi2,  Jesús Camacho1,  Federico Silla1,  José Duato1

1Universidad Politécnica de Valencia, 2Università di Ferrara

12:30 – 14:00, Lunch

 

 

Tuesday, May 4, 2010 (Afternoon)

 

14:00 – 15:30, Auditorium                      ASYNC – NOCS Common Session

Session NA2 : GALS-Based NoC Design

Chair: Davide Bertozzi, Univ. of Ferrara

14:00-14:30

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation [Slides]

Carles Hernández,  Antoni Roca,  Federico Silla,  Jose Flich,  Jose Duato

Universidad Politécnica de Valencia

14:30-15:00

A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors [Slides]

Michael N. Horak1,  Steven M. Nowick2,  Matthew Carlberg3,  Uzi Vishkin4

1Advanced Simulation Technology, Inc., 2Columbia University, 3UC Berkeley, 4University of Maryland

15:00-15:30

Asynchronous Bypass Channels : Improving Performance for DVFS and GALS NoCs [Slides]

Tushar Jain,  Paul Gratz,  Alex Sprintson,  Gwan Choi

Texas A&M University

15:30 – 16:00, Coffee Break

16:00 – 17:30, Small Hall                                ASYNC      

16:00 – 17:30, Auditorium                            NOCS


Session A3 : Embedded Invited Session: Start-ups in Asynchronous Design


Chair :
Alex Yakovlev,
Newcastle Univ.

16:00-17:00


Proteus: Demonstrating Automated Design of GHz Asynchronous Circuits through a High-Density Next-Generation Low-Latency Ethernet Switch Chip [Slides]

Peter A. Beerel and Georgios D. Dimou,
Timeless Design Automation
Andrew M. Lines,
Fulcrum Microsystems

Session N3 : Router Design

Chair: Jose Flich, Universidad Politecnica de Valencia

16:00-16:30

Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs [Slides]

Hiroki Matsutani1,  Michihiro Koibuchi2,  Daisuke Ikebuchi3,  Kimiyoshi Usami4,  Hiroshi Nakamura1,  Hideharu Amano3

1The University of Tokyo, 2National Institute of Informatics, 3Keio University, 4Shibaura Institute of Technology

16:30-17:00

Design of a High-Throughput Distributed Shared-Buffer NoC Router [Slides]

Rohit Sunkam Ramanujam1,  Vassos Soteriou2,  Bill Lin1,  Li-Shiuan Peh3

1University of California, San Diego, 2Cyprus University of Technology, 3Princeton University

17:00-17:15

Soft-Error Handling in On-Chip Networks [Slides]

Young Hoon Kang,  Taek-Jun Kwon,  Jeff Draper

Univ. of Southern California/Information Sciences Institute

17:15-17:30

A 128x128x20Gbp/s Crossbar, Interconnecting 128 Tiles in a Single Hop, and Occupying Less than 5% of Their Area [Slides]

Giorgos Passas,  Manolis Katevenis,  Dionisis Pnevmatikatos

FORTH-ICS, GREECE

17:30 – 18:30 : ASYNC – NOCS Poster Session (Posters of Tuesday presentations)

 

 

Wednesday, May 5, 2010 (Morning)

 

9:00 – 10:00, Auditorium

2nd Keynote

Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized Computing [Slides]

Pr. Keren Bergman, Columbia University

Session Chair : Ran Ginosar, Technion

10:00 – 10:30, Coffee Break

10:30 – 12:00, Small Hall                              ASYNC        

10:30 – 12:00, Auditorium                            NOCS

Session A4 : Low-power and Harvesting

Chair : Laurent Fesquet, TIMA

10:30-11:00

Minimum-Energy Sub-Threshold Self-Timed Circuits:      Design Methodology and a Case Study [Slides]

Omer Can Akgun1, Joachim Rodrigues1 and Jens Sparsø2

1Lund University, 2Technical University of Denmark

11:00-11:30

Static Power Reduction Techniques for Asynchronous Circuits [Slides]

Carlos Otero, Jonathan Tse and Rajit Manohar

Cornell University

11:30-12:00

Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems [Slides]

Jean-Frederic Christmann1, Edith Beigne1, Cyril Condemine1, Pascal Vivet1, Guy Waltisperger1, Jerome Willemin1 and Nicolas Leblond2

1CEA-LETI, 2TIEMPO SAS      

Session N4 : Memory and Efficiency

Chair: Sungjoo Yoo, Postech

10:30-11:00

A Low-Latency and Memory-Efficient On-Chip Network [Slides]

Masoud Daneshtalab,  Masoumeh Ebrahimi,  Hannu Tenhunen

University of Turku

11:00-11:30

Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design [Slides]

David Wolpert,  Bo Fu,  Paul Ampadu

University of Rochester, Rochester, NY USA

11:30-12:00

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs [Slides]

Daniel Gebhardt,  Junbok You,  Kenneth Stevens

University of Utah

12:00 – 13:30, Lunch

 

 

Wednesday, May 5, 2010 (Afternoon)

 

13:30 – 15:00, Auditorium                      ASYNC – NOCS Common Session

Session AN5 : Synchronizers

Chair : Mark Greenstreet, University of British Columbia

13:30-14:00

The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer

William Dally1,2 and Stephen Tell1

1NVIDIA, 2Stanford University

14:00-14:30

Extending Synchronization from Super-threshold to Sub-threshold Region [Slides]

Jun Zhou1, Maryam Ashouei1, David Kinniment2, Jos Huisken1 and Gordon Russell2

1IMEC Netherlands, 2Newcaslte University

14:30-15:00

The Devolution of Synchronizers [Slides]

Salomon Michel Beer, Ran Ginosar, Ruven Dobkin and Avinoam Kolodny

Technion

15:00 – 15:30, Coffee Break

15:30 – 17:00, Small Hall                                ASYNC      

15:30 – 17:00, Auditorium                            NOCS

 Session A6 : High Level Synthesis and Retiming

Chair : Erik Brunvand, Univ. of Utah, USA

15:30-16:00

A fast branch-and-bound approach to asynchronous high-level synthesis [Slides]

John Hansen and Montek Singh

UNC Chapel Hill

16:00-16:30

Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems [Slides]

Gennette Gill and Montek Singh

UNC Chapel Hill

16:30-17:00

Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming [Slides]

Mario R. Casu

Politecnico di Torino

Session N6 : Application-Driven Optimization

Chair: Federico Angiolini, iNoCs

15:30-16:00

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing [Slides]

Nikita Nikitin1,  Satrajit Chatterjee2,  Jordi Cortadella1,  Michael Kishinevsky2,  Umit Ogras2

1Universitat Politecnica de Catalunya, 2Intel Corporation

16:00-16:30

Network-on-Chip Architectures for Neural Networks [Slides]

Dmitri Vainbrand and Ran Ginosar

Technion, Israel

16:30-16:45

Transient and Permanent Error Co-Management Method for Reliable Networks-on-Chip [Slides]

Qiaoyan Yu,  Rabeeh Majidi,  Paul Ampadu

University of Rochester

16:45-17:00

Back Suction: Service Guarantees for Latency-Sensitive On-Chip Networks [Slides]

Jonas Diemer and Rolf Ernst

IDA, TU Braunschweig, Germany

 

    17:00 – 18:30            ASYNC – NOCS Poster Session  (Posters of Wednesday presentations)

                                      ASYNC – NOCS Demonstration Session  (See list of Demos on the Web Site)

19:00 – 23:30

Gala Dinner at “The Bastille”

 

 

Thursday, May 6, 2010 (Morning)

 

9:00 – 10:00, Auditorium

3rd Keynote

Semiconductor Industry: Perspective, Evolution and Challenges [Slides]

Dr. Alessandro Cremonesi – STMicroelectronics

Session Chair : Ahmed Jerraya, CEA LETI

10:00 – 10:30, Coffee Break

10:30 – 12:00, Small Hall                              ASYNC        

10:30 – 12:00, Auditorium                            NOCS

Session A7 : Power-Performance Optimisation

Chair : Montek Singh, UNC Chapel Hill

10:30-11:00

An Asynchronous FPGA with Two-Phase Enable-Scaled Routing [Slides]

Christopher LaFrieda, Benjamin Hill and Rajit Manohar

Cornell University

11:00-11:30

An Operand-Optimized Asynchronous IEEE-754 Double-Precision Floating-Point Adder [Slides]

Basit Riaz Sheikh and Rajit Manohar

Cornell University

 

 

Session N7 : Topology and Architectures

Chair: Paul Ampadu, Univ. of Rochester

10:30-11:00

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-Processor Systems-on-Chip [Slides]

Medardoni Simone1,  Francisco Gilabert2,  Maria Engracia Gomez2,  Davide Bertozzi1

1University of Ferrara, 2Universidad Politecnica de Valencia

11:00-11:30

Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-core NoCs [Slides]

Chia-Hsin Owen Chen1,  Niket Agarwal2,  Tushar Krishna1,  Li-Shiuan Peh1

1MIT, 2Princeton University

11:30-11:45

Design of High-Radix Clos Network on Chip [Slides]

Yu-Hsiang Kao,  Najla Alfaraj,  Ming Yang,  H. Jonathan Chao

Polytechnic Institute of New York University

11:45-12:00

Hierarchical Network-on-Chip for Embedded Many-Core Architectures [Slides]

Alexandre Guerre1,  Nicolas Ventroux1,  Raphaël David1,  Alain Mérigot2

1CEA LIST, 2IEF, Université Paris Sud

 

12:00 – 13:30, Lunch

 

 

Thursday, May 6, 2010 (Afternoon)

 

13:30 – 15:00, Auditorium                      ASYNC – NOCS Common Session

Session NA8 : Emerging Technologies

Chair: Radu Marculescu, Carnegie Mellon University

13:30-14:00

A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Wireless NoCs [Slides]

Ruizhe Wu1,  Yi Wang1,  Danella Zhao1,  Takamaro Kikkawa2       

1University of Louisiana at Lafayette, 2Hiroshima University

14:00-14:30

Power-Efficient and High-Performance Multi-Level Hybrid Nanophotonic Interconnect for Multicores [Slides]

Randy Morris and Avinash Kodi        

Ohio University

14:30-14:45

Performance Evaluation of a Multicore System with Optically Connected Memory Modules [Slides]

Paul Vincent Mejia1,  Rajeevan Amirtharajah1,  Matthew Farrens2,  Venkatesh Akella1        

1Department of Electrical and Computer Engineering, University of California, Davis, 2Department of Computer Science, University of California, Davis

14:45-15:00

Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems [Slides]

Chih-Hao Chao,  Kai-Yuan Jheng,  Hao-Yu Wang,  Jia-Cheng Wu,  An-Yeu Wu                   

National Taiwan University

15:00 – 15:30, Coffee Break

15:30 – 17:00, Small Hall                                ASYNC      

15:30 – 17:00, Auditorium                            NOCS

Session A9 : Arbitration, Delay-Insensitivity, GasP

Chair : Jens Sparsø, DTU

15:30-16:00

Formal Verification of an Arbiter Circuit [Slides]

Chao Yan, Mark Greenstreet and Jochen Eisinger

University of British Columbia

16:00-16:30

Delay insensitivity does not mean slope insensitivity! [Slides]

Florent Ouchet, Laurent Fesquet and Katell Morin-Allory

TIMA (Grenoble INP - UJF - CNRS)

16:30-17:00

Long-Range GasP with Charge Relaxation [Slides]

Swetha Mettala Gilla, Marly Roncken and Ivan Sutherland

Portland State University

Session N9 : Traffic Modeling and Managment

Chair: Ran Ginosar, Technion

15:30-16:00

Distributed Sequencing for Resource Sharing in Multi-Applicative Heterogeneous NoC Platforms [Slides]

Yvain Thonnart,  Romain Lemaire,  Fabien Clermidy

CEA, LETI, MINATEC

16:00-16:30

QuaLe: A Quantum-Leap Inspired Model for Non-Stationary Analysis of NoC Traffic in Multi-Processor Platforms [Slides]

Paul Bogdan,  Miray Kas,  Radu Marculescu,  Onur Mutlu

Carnegie Mellon University

16:30-16:45

Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance [Slides]

F. Palumbo,  Danilo Pani,  Alessandro Pilia,  Luigi Raffo

Dept. of Electrical and Electronic Engineering, Univ. of Cagliari

16:45-17:00

A Network Congestion-Aware Memory Controller [Slides]

Dongki Kim,  Sungjoo Yoo,  Sunggu Lee

POSTECH

    17:00 – 17:30            ASYNC – NOCS Poster Session  (Posters of Thursday presentations)

    17:30 – 18:00            Closing Session and Best paper Awards [Slides]

 

 

Friday, May 7, 2010

 

On Friday 7th May will be organized a full day touring in the Grenoble area. The program will be the following : visit of the Grenoble downtown and historical center with a guide in the morning, a nice lunch in a Grenoble typical restaurant, and in the afternoon visit of the Chartreuse monastery (http://www.chartreuse.fr/pa_correrie_gb.htm), with a final visit of the Voiron Cave (http://www.chartreuse.fr/pa_sommaire_uk.htm) where are produced liquors by monastery monks.

 

This will be a unique opportunity to have a real Grenoble area experience, and to have an extra day in Grenoble to share with conference participants!

 

The organizers reserve the right of cancel the visit in case the number of participants is too low. In that case, reimbursement of the registered participants will be done.

 

 

Saturday, May 8, 2010

 

For people who would like to take advantage of their stay in Grenoble and would really like to enjoy mountain walking in nearby Grenoble Mountains, we propose to organize a one day mountain walking on Saturday 8 May. The idea would be to organize this as a costless event, self organized using our own cars, and we would share the picnic together.

For this, please contact: Cedric Koch-Hofer, (email: cedric.koch-hofer@cea.fr)

According to the number of people we are, and also according to the Saturday weather, various hiking solutions are possible in the close area : Vercors Moucherotte, Belledonne and Chamrousse, Chartreuse Dent de Crolles, …

Do not hesitate to join us ! and do not forget to bring the appropriate shoes and pans.


AEPI