NOCS 2010

Nocs 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
Nocs - Async 2010 Grenoble

The 4th ACM/IEEE International Symposium on Networks-on-Chip - Grenoble, France, May 3-6, 2010

ASYNC - NOCS tutorials

Donwload Call for Tutorials

Monday, May 3, 2010, Tutorials

For our common ASYNC-NOCS 2010 tutorials, we are pleased to present this year 3 full tracks with full-day and half-day tutorials. The program contains 2 tutorials covering NoC topics, and 3 tutorials covering Async topics.

Most of the tutorials will include both theoretical aspects and some challenging practical work. The participants will have the exciting opportunity to do some real lab exercises on computers, using participant’s laptops or desktop computers.

The tutorials will take place in the laboratories of the CIME facilities (Centre Interuniversitaire de MicroElectronique et Nanotechnologies), see, which is located just nearby the MINATEC building.

For better handling of the organisation, and due to maximum capacity of the labs courses, the tutorials will require a minimium of 10 people and a maximum of 30 people. In case a tutorial faces min/max issues, people will be informed and will be invited to participate to an other tutorial.

Tutorial N1   9:00 – 12:30

Tutorial N2   9:00 – 12:30

Tutorial A2   9:00 – 12:30


Virtual Prototyping of 
NoC-based MPSoC:
Fundamentals & Case Studies

(Part I)

Alain Greiner (UPMC/LIP6),

Nicolas Pouillon (UPMC/LIP6),

Frédéric Pétrot (INPG/TIMA),

Fabien Colas-Bigey (Thales),

Laurent Maillet-Contoz (STMicro),

Nguyen Huy-Nam (Bull).



Dynamic Power Management of Multi-Core Systems Under Workload- and Technology-driven Variations


Radu Marculescu (Carnegie Mellon Univ)

Umit Y. Ogras (Intel Corp).




A Simulation Tool for the Study of Metastability in SoCs



Tom Chaney (Blendics LLC),

Dave Zar (Univ. Washington).


Room: CIME

Room Minatec, 222+223+224

Room : CIME

                                                                    Lunch, 12:30 – 14:00                

Tutorial N1   14:00 – 17:30

Tutorial A1   14:00 – 17:30

Tutorial A3   14:00 – 17:30


Virtual Prototyping of 
NoC-based MPSoC:

Fundamentals & Case Studies


(Part II)


ASIPIDE: a graphical framework to design and debug GALS systems through simulation and prototyping


Lilian Janin (Univ. Manchester),

Shoujie Li (Univ. Manchester),

Doug Edwards (U. Manchester).



AHMOSE: Asynchronous High-speed Modeling and Optimization Tool-set


Eslam Yahya (INPG/TIMA),

Jeremie Hamon(INPG/TIMA),

Laurent Fesquet (INPG/TIMA).

Room: CIME

Room : CIME

Room : CIME


  • During the tutorials, there will morning (10:30-11:00) and afternoon (15:30-16:00) coffee breaks. All coffee breaks will take place in the MINATEC Grand Salon.

Tutorial N1

Virtual Prototyping of NoC-based MPSoC:
Fundamentals & Case Studies
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Alain Greiner (UPMC/LIP6),
Nicolas Pouillon (UPMC/LIP6),
Frédéric Pétrot (INPG/TIMA),
Fabien Colas-Bigey (Thales),
Laurent Maillet-Contoz (STMicroelectronics),
Nguyen Huy-Nam (Bull),

Full day, including an hour and a half practical exercises in lab

Virtual prototypes, NoC based architecture exploration,

Target audience:
Engineers and project managers involved in the design of embedded systems, with a background in digital systems design, including hardware and software. The participant are expected to be MPSoC architects and software integrators, for which hardware/software tradeoffs and early performance estimation and software validation are of primary concerns.

As SystemC itself, the SoCLib virtual prototyping platform that will be used to illustrate the ESL design concepts and methods is an open plat-form, available as open-source software, that can be downloaded by the participants, without any extra-costs than the tutorial fee itself.

Platform based virtual prototyping offers the prospect of improving both the productivity and the quality of digital systems development. Designing at higher levels of abstraction is an obvious way as it allows to cope with the system design complexity, to verify earlier in the design process and to increase code reuse.
The tutorial will provide a comprehensive introduction to ESL design and Virtual Prototyping of NoC based MPSoCs. Basic definitions, key concepts, will be introduced. Both industrial and academic case studies will be presented. Our aim is for attendees to learn about ESL design techniques (platform based design, Transaction Level Modeling, virtual prototyping, design space exploration…). The design methods will be illustrated on a public domain platform, but the tutorial will give a view of the directions the industry is taking for the longer term.
The public domain SoCLib platform is a SystemC-based virtual prototyping environment funded by the French authorities. Six industrial companies (including Thales, ST Microelectronics & Orange)  and 10 academic laboratories joined to build this open modeling and simulation environment. The project leader is Thales, and the technical coordination is done by the LIP6 laboratory. The SoCLib platform ( will be used to illustrate the concepts. This infrastructure is already used in France by a large number of laboratories, and several large industrial companies.

Schedule & Content:
The proposed tutorial is structured in three parts, requiring a full day : The basic principles of virtual prototyping will be presented in the morning. Three use cases will be presented in the afternoon, as well as a practical work using a bootable LiveCD and either the participants laptops or desktop computers provided by the CIME-Nanotech facilities.

Virtual Prototyping principles

  • Virtual prototyping with TLM2.0 (Laurent Maillet-Contoz : STMicro)                  30’
  • SystemC, and the various abstraction levels for NOC-based MPSoC modelling, the corresponding simulation algorithms and the VCI/OCP Communication standards (Alain Greiner : LIP6)                                                                                          90’
  • Design Space exploration & mapping tool (Nicolas Pouillon : LIP6)                           30’

Use cases

  • Modelling an H264 decoder   (Fabien Colas-Bigey : Thales)                             30’
  • Performance evaluation of a multi-core architecture (Nguyen Nam: Bull)           30’
  • Prototyping an hardware-based page migration mechanism on a NoC-based
    shared memory multicore architectures (Frederic Pétrot  : TIMA)                     30’

Practical Exercises

Exercises relying on simulation models and tools available in SoCLib platform.           90’

A bootable LiveCD will be distributed to the participants, that will use either their own laptop or the computers of the CIME-Nanotech to simulate a multi-processor architecture modelled with SoCLib and running a multi-threaded software application (MJPEG decoder). The same binary code will be successively executed on virtual prototypes described at various abstraction levels (Transactional, Transactional with distributed time and cycle-accurate/bit-accurate).

All proposed speakers (3 academic and 3 industrial speakers) have been involved in the SoCLib project and are major contributors to this virtual prototyping platform. The tutorial will be organized and coordinated by professor Alain Greiner.

  • Alain Greiner (UPMC/LIP6)

Alain Greiner is a Professor in computer science at Université Pierre et Marie Curie in Paris. He is the head of the SoC department of the LIP6 laboratory. He was the inventor of the first published network on Chip, in 2000 (SPIN). He is presently interested in methods and tools for multi-processor system on chip, and  is the technical coordinator of the SoClib project.

  •          Frédéric Pétrot (INPG/TIMA)

Frederic Petrot is a Professor in Computer Science at Ensimag in Grenoble, and heads the System Level Synthesis group of the TIMA laboratory. While previously Assistant Professor at University Pierre et Marie Curie, he was a major contributor to the Alliance CAD System, and he headed the design and development of the Dysident toolset. Fred's research interests currently focus on the design and implementation of MPSoC architectures and simulation strategies at different level of abstraction for these SoCs.

  •          Fabien Colas-Bigey (Thales)

Fabien Colas-Bigey belongs to the "Advanced Architecture Laborary" of the Radio and Signal Technical Business unit in Thales Communications since 2005. His main field of expertise is the development of heterogeneous systems in SystemC. He's been working on R&D projects aiming at improving methodologies and tools used in the development of high-level system models. Fabien is in charge of the general management of the SoCLib project on behalf of the Thales company.

  •          Laurent Maillet-Contoz (STMicroelectronics)

Laurent Maillet-Contoz is CAD Manager at STMicroelectronics, heading the transaction-level modeling (TLM) activity in the System Platforms Group. He has been involved in the definition of the TLM methodology within ST from 2000, and has contributed to the definition of the OSCI TLM standards. He is currently the ST Representative to the OSCI Board of Directors. His main interests are system modelling and simulation, and formal methods for SoC verification.

  •          Nguyen Huy-Nam (Bull)

Nguyen Huy-Nam is responsible of the MVS team at Bull/SDD. His domains of interest include Protocol design and validation, High-Level Modelling, Formal Verification, System prototyping. Nam is the project leader of the TSAR Medea+ project which targets the design of a scalable, shared memory multi-cores architecture, using the SoCLib infrastructure for virtual prototyping.

  •          Nicolas Pouillon (UPMC/LIP6)

Nicolas Pouillon is a research engineer at LIP6 Laboratory. He is the main developer and integrator of the SoCLib virtual prototyping plat-form.

Tutorial N2:

Dynamic Power Management of Multi-Core Systems
Under Workload- and Technology-driven Variations
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Radu Marculescu (Carnegie Mellon University),
Umit Y. Ogras (Intel Corp).

Half day tutorial.

Multi/many-core platforms, Multi-clock/voltage domains, Systems-on-Chip, Chip Multiprocessors, Networks-on-Chip, Globally Asynchronous Locally Synchronous, Low-power, Variability.

Target audience:

This tutorial is intended for an audience relatively new to the design and optimization techniques for power- and variability-aware of multi-core systems, with a minimal background in VLSI and design automation techniques. The presentation will introduce the relevant 1 background material, give an overview of the current state-of-the-art results in VFI and GALS alternative for designing the communication infrastructure, and finally, talk about run-time resource optimization and dynamic power management issues in the presence of parameter and workload variations. The material discussed in this tutorial is highly relevant to system designers and software developers interested in the future of multi- and many-core systems.

Continuous technology scaling allows hundreds of processing cores integrated on the same chip; this represents the multiprocessor system-on-chip (MPSoC) paradigm which makes it possible to run multiple heterogeneous applications concurrently on a single chip. However, on- chip power consumption represents one of the main bottlenecks in providing increased performance and enhanced capabilities for such platforms. Indeed, increased power consumption results not only in higher on-die temperature and reduced lifetime reliability, but also leads to faster discharge of battery-powered mobile devices. On-chip power management is therefore a critical component of run time MPSoC optimization in presence of workload and process-driven variations.  Power management techniques for individual cores are well established. For example, current commercial products support numerous sleep and performance states. However, orchestrating the power management many processing cores interconnected by an interconnection network is relatively untouched. The multiple voltage and frequency island (VFI) design style with support for dynamic voltage and frequency scaling (DVFS) was recently proposed as an effective paradigm to deal with application heterogeneity in highly parallel MPSoCs. Such systems are divided into multiple VFIs where the voltage and frequency of each island in the system can be set independently of all other islands and adapt at run-time in response to temporal variations in application characteristics.  Starting from these overarching ideas, this proposal addresses the fundamental issue of designing effective and highly scalable DVFS control algorithms able to regulate the voltage and frequency of the VFIs in MPSoCs with hundreds or thousands of cores in response to application heterogeneity and process-driven variations. In order to understand the challenges and opportunities in this problem space, this tutorial presents a comprehensive review of advanced design techniques in multi-domain clock and power management for high-performance processors, as well as low power systems-on-chip (SoCs).

Scalable and complexity-effective power management mechanisms require accurately accounting for the complexity and overhead of mechanisms used for adaptive voltage and frequency scaling, while guaranteeing certain levels of power/performance under increased workload- and process- driven variations. These mechanisms need also take the correlations between different processing cores and orchestrate power management at the system level as opposed to local DVFS solutions.  For example, some resources can be freed by to enable turning of parts of the system, or the speeds of different subsystems can be tightly controlled for energy efficient operation. To this end, we also look into fundamental limits on the performance of such control algorithms for power management due to the challenges introduced by technology scaling, including process variations.

Outline :

  1. NoC Design Overview
  • Multi-domain processors
  • Router design and synchronization issues
  • Industrial and academic examples: Intel 80-core and SCC 48-core designs.
  1. Control and Power Management in Presence of Workload Variations
  • Multiple voltage-frequency island (VFI) design
  • VFI partitioning and workload modeling
  • Dynamic control of multi-VFI designs: Centralized vs. distributed control
  1. Robust Design and DVFS Control in Presence of Process Variations
  • Impact of process variations on DVFS controller performance
  • Technology-driven limits on DVFS controllability
  • Looking ahead: Leakage variations in NoCs, 3D NoCs, etc.

Radu Marculescu is a Professor in the Dept. of Electrical and Computer Engineering at Carnegie Mellon University, USA. He received his Ph.D. in Electrical Engineering from the University of Southern California in 1998. He has received the Best Paper Award of IEEE Transactions on VLSI Systems in 2005, as well as several best paper awards in major conferences in the area of design automation. Dr. Marculescu has been involved in organizing many international symposia, conferences, workshops, and tutorials, as well as guest editor of special issues in archival journals and magazines. His research focuses on design methodologies and software tools for system-on-chip design, on-chip communication, and ambient intelligence. Radu Marculescu is an ACM Distinguished Speaker (2009-2010).
Umit Y. Ogras is a research scientist in Intel Strategic CAD Labs. He received his Ph.D. degree in  Electrical and Computer Engineering at Carnegie Mellon University. He received the 2008 EDAA  outstanding dissertations award. His research interests are in the areas of embedded systems and  electronic design automation. In particular, his research focuses on communication-centric design  methodologies for nanoscale SoCs, with a special interest on Networks-on-Chip communication architectures.

Tutorial A1

ASIPIDE: a graphical framework to design and debug
GALS systems through simulation and prototyping
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Lilian JANIN, Shoujie LI, Doug EDWARDS
{lilian.janin,, doug.edwards}
IT302, School of Computer Science
The University of Manchester
Manchester M13 9PL

Half day with labs.

GALS, virtual platform, simulation, debugging, NoC

Target audience:

Anyone interested in GALS design and virtual platform, with or without NoC, at levels of abstractions ranging from SystemC to RTL. No pre-requisite apart from very basic knowledge of Verilog and SystemC.

This tutorial will reveal the capabilities of the ASIPIDE framework, developed as part of the European Framework 7 GALAXY project ( ASIPIDE is an integrated environment of development for GALS systems based around the following key ideas:

  • Guiding users in the design of GALS systems, by automating the suggestion and placement of GALS adapters, and by making debugging and optimizations through simulation easier thanks to advanced visualization techniques.
  • Allowing components at any levels of abstraction and any description languages to be simulated seamlessly together, with an automatic generation of the co-simulation interfaces.
  • Being an extensible platform easing the integration of existing tools.
  • Open-source tools, in particular, can be brought together as complete tool flows.
  • Thanks to the integration of University of Bologna’s XPipes, networks on chip can also be graphically designed, inspected and optimised.

The aim of the GALAXY project is to provide an integrated GALS (Globally Asynchronous, Locally Synchronous) design flow, together with novel Network-on-Chip capabilities, that will materially aid embedded system design for a significant class of problems. We aim to remove existing barriers to the adoption of the technology by providing an interoperability framework between the existing open and commercial CAD tools that will support development of heterogeneous systems at the different levels of abstraction. Our project partners will evaluate the ability of the GALS approach to solve system integration issues and, by implementing a complex wireless communication system on an advanced 45nm CMOS process, explore the low EMI properties, inherent low-power features and robustness to process variability problems in nanoscale geometries.

Outline :
1. General presentation of the tools and IDE:

  • Rapid design and prototyping (example of drag&drop-based incremental design co-simulated in software + FPGA).
  • Ability to handle large designs (G3card system, simulation trace, link to source code)

2. Presentation of individual features (unrelated targeted examples)

  • Automatic instantiation of adapters (width, protocol and GALS adapters)
  • Automatic use of transactors
  • Ability to use any simulator or FPGA target (ability to use asynchronous‐specific simulators: balsa, petri nets)
  • Many supported languages, and extensible to new ones
  • Easy to switch components between multiple levels of abstractions, with always a proper interface regenerated
  • Automatic use of local and remote tools for compilation, synthesis and simulation flow; remote resource sharing (queues)
  • Trace file animation, debugging (colour-based channel representation, clearer and saving space; asynchronous debugging such as deadlock detection)
  • Network on chip abstract view, XPipes implementation: automatic NoC generation.

3. Interactive hands-on

  • Exercise 1: GALSification

We provide a synchronous example, which the user will GALSify using the ASIPIDE framework.

  • Exercise 2: Design refinement and NoC

We provide a design at a high level of abstraction, which the user will refine incrementally to low level, and will finally add a NoC interconnect able to work across multiple abstractions.

Lilian Janin is a Research Associate in the Advanced Processor Technologies Group, School of Computer Science at the University of Manchester, where he received his PhD degree in 2004. His current research interests are in the simulation and visualization of complex systems.
Shoujie Li is a Research Assistant in the School of Computer Science at the University of Manchester, UK. His current research interests include GALS systems, wireless communication. His past work was in radio access network design and radar systems.
Doug Edwards is a Reader in Computer Science at the University of Manchester, UK. His current (overlapping) research interests include synthesis of asynchronous systems, network-on-chips and GALS technology. Previous research work has been in the areas of high speed optical fibre LANs, formal hardware verification, PCB routing accelerators and in the distant past, research into blue light emitting hetero-junction structures.

Tutorial A2

A Simulation Tool for the Study of Metastability in SoCs
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Tom Chaney,, Blendics LLC
Dave Zar,, Washington University

Half day, including an hour hands-on demonstration in lab

Metastability, operating corners, MTBF, synchronizer, arbiter, SoC

Target audience:

SoC designers, both commercial and academic

The Mean Time Between Failures (MTBF) of synchronizers has become an issue of increasing importance as circuits move to nano-scale processes. There are more synchronizers on giga-transistor chips and their metastability time constants do not scale well. Circuit variability within a wafer increases as the industry moves to deeper sub-micron processes. Transistor aging jeopardizes the integrity of synchronizers in chips that must perform over an extended lifetime. The usual assumption that data and clock are statistically independent fails when clocks are derived from different PLLs, but use the same oscillator. This circumstance results in the possibility of repeated malicious inputs to synchronizers.
For all these reasons it is increasingly important to analyze synchronizer failures before SoC fabrication in order to avoid re-spins and verify the correct performance of synchronizer arrays at operating corners of process, voltage, temperature and aging. This tutorial builds on the ASYNC 2008 tutorial by Kinniment, papers by Yang and Greenstreet and recent work at Blendics. We will describe the relationship between a circuit description and the improbable behaviors of that circuit including: (1) circuit asymmetry, (2) circuit non-linearity, (3) common-mode effects, (4) trailing clock-edge issues (5) circuit noise, (6) the cross-checking of results, and (7) process scaling. Utilizing these observations and relationships we have developed a tool, called MetaACE. It augments a popular IC circuit simulator to facilitate the analysis of metastability hazards in both ASICs and FPGAs. The operation of MetaACE will be explained and demonstrated.
The relationship between simulation and physical measurements will also be discussed as will bounds on MTBF that apply when malicious synchronizer inputs are present. There will always remain some uncertainties in any metastability analysis and these sources of risk will be identified and discussed.


  • Trends that make metastability an emerging issue in SoC design
  • History of investigations into metastability
  • Models of circuits in metastability
  • Mean time between failures (MTBF)
  • Uncertainties and problems in metastability analysis
  • Circuit asymmetry
  • Effects of non-linearity
  • Simulator limits on precision
  • Common-mode effects
  • Trailing clock-edge issues
  • Circuit noise
  • Multiple metastable node-pairs in a complex circuits
  • Relationship to physical measurements
  • MetaACE: A circuit simulator for understanding metastability
  • Finding circuit constants τ and Tw from node traces
  • Finding circuit constants τ and Tw from failure window and stabilization times
  • Advantages and disadvantages of two approaches
  • Bisection to investigate improbable events
  • Example circuits and effects of PVTA corners
  • Example of MTBF for uniform distribution and for thermal noise bound
  • Effects of process scaling on MTBF
  • Demonstration of the operation of MetaACE on an example circuit

Hands-on lab for interested registrants to follow tutorial and demonstration

Tom Chaney received his MS in Electrical Engineering from Washington University (1969) and participated in the Macromodular Computer Design project from 1965 to 1974 during which time he published the first measured data on synchronizer failures. He has been recognized as an expert in the field over the intervening years.
Dave Zar received his MS from WU in 1993 and has taught courses at Washington University in digital system design, including the issues surrounding metastability between 1993 and the present. He is one of the developers of MetaACE and is supported through a NSF sub-award from Blendics to Washington University. This work has been supported in part by grant 0924010 from the US National Science Foundation.

Tutorial A3

AHMOSE: Asynchronous High-speed
Modeling and Optimization Tool-set
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Eslam Yahya, Jeremie Hamon, Laurent Fesquet
CIS Group
Grenoble, France

Half day tutorial, with labs.

Asynchronous Circuit, Performance Analysis and Optimization, Process Variability.

Target audience:

The tutorial concerns performance modeling, analysis and optimization of asynchronous circuits. By using high level of abstraction, a delay variability aware methods and tools are proposed. This tutorial is targeted to designers interested in performance analysis and optimization. Timing performance, power consumption distribution, EMI and handshaking protocol effect will be covered in the tutorial.

AHMOSE tools are new performance analysis and optimization flow. Starting from high level of abstraction, fast (but still accurate) estimations for asynchronous circuits’ performance are calculated. This tutorial introduces the use of AHMOSE for:

  • Statistical Timing analysis of asynchronous circuits. By using the underlying methods, general structures including choices are analyzed. All analysis are done while considering timing variability.
  • Event distributions of the circuit which indicates the power and EMI characteristics.
  • The Effect of handshaking protocol on different performance metrics.  
  • Automatically optimize asynchronous structures by optimally place registers to meet the required cycle time.


  1. Brief presentation of the underlying methods

In this presentation, the key ideas of the underlying methods are explained. Issues related to modeling and levels of abstraction are discussed. Finally, a general overview of the tool flow is presented to prepare the audiences for using the tools.

  1. Introduction to the flow by using simple examples

Starting from the circuit block diagram, attendees will derive the equivalent model and implement it using the GUI.  Step by Step, they will explore the tool flow till they end with analysis results.

  1. Exercises:
  • Timing analysis

In this example, the users will generate the delays of the circuit components by using the delay generator. By means of the GUI, different delay distributions are assigned to the circuit components. After that, the different timing metrics are analyzed

  • Process variability Effect

Monte Carlo analysis will be used to analyze process variability (WD and DD) in some circuit. The same circuit is analyzed by using AHMOSE and results are compared in terms of computation time and accuracy

  • Circuit activity analysis

In this exercise, users will analyze the circuit activity. The time distribution for the circuit events are drawn by using the new flow. That would help for detecting system parts which have high activity, equivalently high power consumption

  • Effect of handshaking protocol

By using the previous examples, users will change the used handshaking protocol and inspect the effect on speed, activity and process variability effect on the output

  • Optimization of Asynchronous links

Some asynchronous link is analyzed and optimized. The user will define different cycle time constraints and automatically place the necessary registers inside the circuit

Eslam Yahya is a post-doctorate researcher in the CIS group at TIMA; he received his PhD in 2009. His current research interests are modeling, design and optimization of asynchronous circuits; encryption; asynchronous oscillators; Complex SOC design techniques and CAD tools.
Jeremie Hamon is assistant professor at the Grenoble Institute of Technology and a post-doctorate researcher in the CIS group at TIMA. He received his PhD in 2009. His main research activity with the TIMA Laboratory is the study of clockless systems for digital communication, and more specifically, for ultra-wideband (UWB) impulse radio communication for wireless sensor networks.
Laurent Fesquet is associate professor at the Grenoble Institute of Technology and team leader of the CIS group at TIMA. His works address circuit design, Complex SOC design techniques, CAD tools for asynchronous circuits and signal processing for non-uniformly sampled signals.