Hardening energy efficient security features for the IoT in FDSOI 28nm technology

Published : 11 January 2019

The security of the IoT connected objects must be energy efficient. But most of the work

around hardening by design show an additional cost, a multiplying factor of 2 to 5, on the

surface, performance, power and energy, which does not meet the constraints of the IoT.

Last 5 years research efforts on hardening have been guided by reducing silicon area or

power, which do not always imply a decrease in energy, predominant criterion in autonomous

connected objects. The postdoc topic addresses the hardening and energy consumption

optimization of the implementation of security functions (attack detection sensors,

cryptographic accelerator, random number generator, etc.) in 28nm FDSOI technology.

From the selection of existing security bricks, unhardened in FPGA technology, the postdoc

will explore hardening solutions at each step of the design flow in order to propose and

to validate, into a silicon demonstrator, the most energy efficient countermeasures that

guarantee a targeted security level.

To achieve those goals, the postdoc can rely on existing methodologies of design and of

security evaluation thanks to test benches and attack tools.

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