Modeling silicon-on-insulator quantum bits

Published : 15 July 2019

Quantum information technologies on silicon have raised an increasing interest over the last five years. CEA is pushing forward its own original platform based on the “silicon-on-insulator” (SOI) technology. The information is stored in the spin of carrier(s) trapped in quantum dots, which are etched in a thin silicon film and are controlled by metal gates. SOI has many assets: the patterning of the thin film can produce smaller, hence more scalable qubits; also, the use of the silicon substrate beneath as a back gate provides extra control over the quantum bits (qubits).

Many aspects of the physics of silicon spin qubits are still poorly understood. It is, therefore, essential to complement the experimental activity with state-of-the-art modeling. For that purpose, CEA is actively developing the “TB_Sim” code. The aims of this 2-year post-doctoral position are to model spin manipulation and readout in SOI qubits, and to model decoherence and relaxation at the atomistic scale using TB_Sim. This modeling work will be strongly coupled to the experimental activity in Grenoble. The candidate will have access to experimental data on state-of-the-art devices.

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