Cryogenic electronics to massively address silicon quantum bits
Published : 8 February 2020
Research on quantum computing currently focuses on upscaling the number of qubits in order to reach useful calculation capabilities. The mature CMOS technology for circuits offers the opportunity to develop on-chip integration of CMOS spin-qubits together with classical electronics. Readout chips at sub-Kelvin temperatures form a key element in the massive addressing of a qubit matrix compared to nowadays solutions with cable-limited room-temperature instruments. Our previous studies on circuits made with the industrial 28-nm Fully Depleted Silicon on Insulator technology have demonstrated the operation of basic circuit elements down to temperatures as low as 20 mK with acceptable power dissipation. Using this toolbox of cryogenic circuits, the thesis concentrates on the design and operation of more complex cryogenic circuits in order to massively address CMOS-inspired qubits matrix at low temperatures. The ultimate goal is to readout 1000’s of spin qubits in a line-column arrangement. The PhD student will explore alternative solutions for scalable readout such as the frequency multiplexing of electrometer sensors or of resonant oscillating circuits.