Design of a 3D stacked smart imager dedicated to neural network processing

Published : 8 February 2020

The 3D stacked silicon technologies allow the fabrication of new kinds of smart vision sensors by vertically coupling image sensor and specific processors or memories inside the same chip. Some research teams develop 3D stacked vision chip either to increase the quality of the sensor or to embed high powerful processors inside the chip closely coupled to the imager, as we did by developing the RETINE chip. Deep neural networks are widely used in many application domains including computer vision. A lot of research consists in increasing the power efficiency and decreasing the power consumption of embedded systems dedicated to neural networks execution. In this PhD thesis we propose to evaluate the opportunities offered by 3D stacked silicon technologies to question and envision new kind of digital 3D stacked vision chip embedding neural network hardware.

In this PhD thesis we wish to study the contribution of 3D integration technologies in an intelligent imager integrating neural network processing functions. We will focus this study mainly on deep neural networks, however other types of neural networks can be evaluated.

The architectural contribution expected from this thesis is the study and design of an efficient and low-power computing architecture that meets the high constraints imposed by deep neural networks, namely the need for very regular high-performance computing and the very high need for memory

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