Development and characterization of ferroelectric layers for the fabrication of FeFET transistors
Published : 10 January 2019
Permanent progression of electronic devices requires that their components must be constantly adapted. The current memories are based on Phase Change Memory (PCM) architectures, but they need high power to work. The introduction of ferroelectric materials would enable to create memories working with lower voltages and therefore being more adapted to technologies requiring low consumption (mobile applications for instance). The main feature of these materials is their ability to keep a residual polarization at null field. This polarization can be reversed thanks to an external electric field. So, it is possible to match the two states of polarization with the two logical states of a transistor (“passing” and “blocking”), fundamental element of the memories.
This thesis aims to analyze this ferroelectric material to introduce them in future generations of memories. A bibliographic study will allow to set up a design of experiments to fabricate these layers by Atomic Layer Deposition (ALD). Next, these depositions will be characterized according to several factors like the ferroelectricity, the crystal structure or the composition. Optimal conditions to satisfy a high polarization of the material will be deducted from this analyze. The integration of the layers in the associated transistors will mark a second step of the thesis. This one will mainly allow to validate the proper functioning of this so-called transistors FeFET, but also to study the interface between the ferroelectric oxide and the canal of the transistor. This study of the interface, supported by thermodynamic and kinetic simulations, will ensure that the electric charges do not come to accumulate, which would impact the functioning of the transistor.