Exploring the scalability of spintronics for 3D devices
Published : 15 July 2019
Classical microelectronics is reaching its limits of downward scalability, reaching technological or scientific bottlenecks. Magnetic random access memories, based on magnetic tunnel junctions storing and reading bits of information, are emerging key ICT components. They are of immediate relevance for low-power and high-speed processor and mass-storage cache memory. Similar to other technologies, ways are being searched to design threedimensional devices and thus allow long-term scalability in terms of areal density.
The scalability of single MRAM cells below 10nm lateral size has been demonstrated in the lab recently, independently at SPINTEC and at Tohoku university. The purpose of this PhD is to pave the way towards integration of this concept in a viable technological process, compatible with high areal density and mass production. The principle relies on filling semiconductor vertical interconnects with a magnetic material, to be used as a storage cell. The first steps will consist in the structural, magnetic and electric characterization of such interconnects. At the scale of a PhD the work will be extended to fully functional memory cell, addressing both fundamental and technological challenges. This topic is a joint action between Spintec and LETI.