High speed wireline and optical communication at cryogenic temperature for quantum computing

Published : 8 February 2020

The promise for a universal fault-tolerant quantum computer robust to relaxation and phase errors of qubits faces a major scaling challenge, with thousands to millions of qubits to control and measure to implement the necessary quantum error correction codes. The information to exchange between the quantum devices at cryogenic temperature and the room temperature instrumentation equipments needs data throughputs above 1 Terabit/s to achieve in a reduced power budget to limit self-heating. This PhD topic aims to propose and realize energy-efficient high-speed communication architectures and circuits leveraging optical fiber transmission between the cryostat and the ambient temperature.

The targetted innovation is to design and implement cryo-electronic CMOS circuits in FDSOI technology to realize communication functions such as SerDes, clock recovery and silicon-photonic modulator and receiver drivers tightly coupled to the quantum devices.

These works will be integrated in a large development effort for a quantum computing Accelerator architecture based on electron spins in silicon, led by a pluridisciplinary team of physicists, technologists, CMOS designers and hardware and software architects.

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