Impact of micro-architecture on side-channel attack countermeasures

Published : 8 February 2020

The context of this thesis is the context of cyber-security for embedded systems and IoT. The thesis addresses the application of countermeasures by compilation against side-channel attacks exploiting power consumption or electromagnetic emissions, which represent a major threat against these systems.

A leakage model can be used when applying countermeasures: it models how side-channel leakages are related to the program and the data being manipulated by the processor. An unfaithful model does not allow the countermeasure to be applied effectively. The models currently employed are insufficient since they do not take into account the micro-architecture of the components. Indeed, micro-architecture and in particular elements that are invisible at the assembly level (hidden registers or buffers) can cause leakages.

The objective of this thesis is to study the impact of micro-architecture on the automated application of countermeasures against auxiliary channel attacks during compilation. A first axis is to study how to modify the way countermeasures are applied within the compiler to take into account precise leakage models that are micro-architecture aware, for example how to adapt the instruction selection or register allocation in the compiler depending on the leakage model. A second axis is to adapt the countermeasures themselves in order to better take into account the nature of the leakages, with the objective of improving the reduction of information leakage and thus improving the security/performance trade-off.

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