Low Level Programming model for not “Von Neumann” architecture

Published : 10 January 2019

Since the 60s the programming model used by processors is the “Von Neumann” model in which a processor will look for instructions and data to be processed in the same memory. Increasing the transistor density on a chip has increased its frequency but has produced a “bottleneck” to the memory that can not provide instructions and data at the same frequency : the memory wall.

Many architectural solutions have been proposed to solve this bottleneck. One of the solutions we are studying is an architecture in which calculations are made in memory, without moving the data to the processor. The evaluation of this solution has shown impressive potential gains in speed (x10000) and energy (x30).

To exploit this potential, it is necessary to change the programming model because the instructions will no longer be read in memory but generated by a processor that will drive one or more memory plane.

The subject of the thesis will be the compilation of a high-level language to a flow of instructions interleaving processor instructions responsible for controlling and calculating addresses and instructions for controlling calculations in memory.

This subject is a part of a bigger project in which we create a system composed of processor and computing memory.

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