Strain engineering for 12nm FDSOI technology and beyond
Published : 27 February 2019
Strain engineering is a major tool to boost the performance of transistors. Tensile strain increases electron mobility and compression improves holes mobility. Hole mobility is also favored by the use of SiGe channel. In advanced FDSOI the co-integration of Si channels for nMOS and and SiGe channels for pMOS is done by the transformation of the top-Si layer into SiGe via Ge condensation. For this, an epitaxy of a SiGe is done on a selected Si area. During thermal oxidation, Ge atoms are rejected into the underlying Si layer. The buried-oxyde (BOX) of the SOI wafer acts as a diffusion barrier for Ge, the result is a local SiGe-On-Insulator (SGOI) substrate. The SiGe film is obtained such as it keeps the in-plane lattice parameter of Si and therefore is found under biaxial compressive strain in the plane of growth. Today, the condensation technique allows a co-integration of Si-based nMOS and compressively strained SiGe-based pMOS transistors.
The Problem: when the cSiGe made by Ge-condensation is discontinued for the fabrication of the STI, a local elastic relaxation of the compressive stress close to the STI edge is naturally expected. However, experiments show more than elastic relaxation over large distance from the STI discontinuity causing a significant loss of compressive strain in the layer, and therefore, a lower contribution to the performance of devices. In summary, the physical mechanisms behind this behavior are unknown today and of major impact on advanced CMOS. This work is aimed to bring light on this subject and propose/develop technologycal solutions.