System-level simulation and exploration flow for non-volatile neuromorphic architectures

Published : 15 July 2019

Hardware neural network implementation is a hot topic in research and is now considered as strategic for several international companies. Leading projects in neuromorphic engineering have led to powerful brain-inspired chips such as SyNAPSE, TrueNorth and SpiNNaker. Most of these technologies work well in centralized computing farms but will not fit embedded systems or Internet-of-Things (IoT) requirements, due to their energy consumption. Heterogeneous integration between CMOS and emergent technologies is seen as an opportunity to go past this limitation. In particular, Magnetoresistive Random-Access Memory (MRAM) is considered one of the most promising Non-Volatile Memory (NVM) technology expected to mitigate energy consumption when integrated in computing architectures. In order to explore the architectural design space, we still miss a high-level abstraction to quickly assess how NVM actually benefits energy efficiency and how it can be improved any further.

In this context, the aim of the thesis is to enable exploration of NVM-based neuromorphic accelerators by defining a framework for the joint, high-level modelling of digital logic and NVM-based functions. The framework will enable exploration of new architectural choices based on NVM properties to understand how they affect the performance/energy/area trade-off.

The thesis will be supervised by Sébastien Bilavarn (University Côte d’Azur, LEAT, Sophia Antipolis) and co-supervised by François Duhem (CEA/Spintec, Grenoble).

Applicants should have background in RTL development, system architecture, electronics and programming language such as C/C++ (SystemC appreciated).

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