Tunable SOI-CMOS/GaN HPA for 5G infrastructure

Published : 8 February 2020

RF GaN technology has emerged as a strong candidate for high power 5G PA (HPA). The high power density, low output capacitance, and high breakdown voltage of GaN transistors make them attractive for the 5G small-cell market that requires several watts of output power at high frequencies (up to 40GHz). In this Ph.D. work, the student will investigate the heterogeneous SOI-CMOS/GaN Integration of a mmWave high-efficiency HPA. The output stage of the HPA will use Doherty architecture in order to achieve high-efficiency in the back-off region. It will be implemented on GaN to achieve the required power levels. To avoid the performances degradation of the Doherty stage over frequency, the input phase and driver level of the main and auxiliary transistors of the Doherty PA need to be carefully controlled. The driver stage of the Doherty stage will be implemented on SOI technology in order to enable tunability of the drive signals (phase and amplitude) using reconfigurable passives on SOI. This digitally assisted HPA will allow the optimization of both linearity and efficiency over wide frequency range of operation in a compact solution.

This PhD thésis is proposed as an international PhD, diploma from University of Grneoble Alps, in collaboration with a European Partner. This PhD maybe a strong opportunity for the student for mutual collaboration, and a stay abroad.

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