From technology to integrated circuits: optimization and validation of parasitics modeling into PDKs

Context :
Parasitic resistances and capacitances in integrated circuit produce circuit performance degradations (i.e speed and power consumption) when CMOS technologies are scaling down. They also need to be accounted accurately while designing Non Volatile Memory (NVM) advanced circuit for neuromorphic applications or high power circuit with GaN technology to anticipate heating effect. Parasitic elements are evaluated with PEX (Parasitic Extraction) tool which is included into Process Design Kits (PDK). PDK describes a technology and gather the tools necessary to design functional circuits: Design Rules Check (DRC), Layout versus Schematic (LVS), PEX and devices models. PEX development and its validation are not addressed by literature. Indeed, industrial companies perform usually this validation with the post layout simulation comparison with electrical measurements of complex circuits. Obviously, this method is hardly usable in research environment such as in Leti.

Work expected :
The internship objective is to validate the parasitic extraction performed by the parasitic extraction tool included in Leti PDKs. The methodology need to be as generic as possible, to be used on all Leti microelectronics technologies. This work will be performed with experts from the Simulation and Modeling Laboratory (LSM) and from the Mask and Design Kit Laboratory (LMDK). 5 steps are scheduled:
   1. Test structures definition to validate parasitic extraction in the CMOS technology front-, middle-, and back-end
   2. Development of a simplified CMOS PEX and comparison of results obtained with competitor tools: Calibre
       from Mentor and StarRC from Synopsys which are standard tools of industrial companies.
   3. 3D finite elements simulation flow developement with Silvaco Clever tool and comparison of the results obtained from PEX extraction in step 2.
   4. Identification and characterization of available test structures on silicon, compatible with the methodology validation.
   5. Documentation of the methodology to ensure the alignment between pre and post layout SPICE simulations.

If you are interested by the internship, please send your CV and motivation letter to joris.lacord@cea.fr

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