Actualités : Technologies micro et nano

Context : Die-to-wafer stacking is foreseen by major microelectronic industrials as essential for the success of future memory, photonic devices or high performance computing involved in Artificial Intelligence booming. CEA-Leti demonstrated Die-to-Wafer with hybrid bonding which significantly reduces the electrical interconnection pitch compared to standard bonding techniques. Die alignment time is identified as the main […] >>

Cadre et contexte : Afin d’augmenter la capacité des microbatterie lithium à surface de composant constante, l’empilement 3D est la solution à envisager tout en réduisant au maximum les parties passives du composant (wafer, intercos, scellement). L’objectif du stage est de développer et valider des briques technologiques nécessaires à cet empilement Travail demandé : Réalisation […] >>

Context : 3D sequential integration enables to achieve the highest 3D contact density between stacked levels compared to other existing techniques. However it requires to process stacked devices with a limited thermal budget. Leti institute is pioneer in this domain and has a unique expertise on low temperature devices for computing applications. This internship’s goal […] >>

Context : Parasitic resistances and capacitances in integrated circuit produce circuit performance degradations (i.e speed and power consumption) when CMOS technologies are scaling down. They also need to be accounted accurately while designing Non Volatile Memory (NVM) advanced circuit for neuromorphic applications or high power circuit with GaN technology to anticipate heating effect. Parasitic elements […] >>

Context : Because it may revolutionize the high performance computing systems, nowadays, silicon quantum computing technologies receive an increasing interest. Based on quantum bit (Qubit), the large potential of those technologies stems from the use of CMOS know-how to adapt the semiconductor qubit in large scale. To achieve efficient control and read-out of qubit with […] >>