Electrical characterization and study of carrier transport in new generation transistors fabricated from III-V materials (InGaAs)
Offer N°: SL-DRT-16-0319
The topic of this thesis is related to the Research effort in more Moore domain to pursue CMOS technology nodes beyond 7nm.
RRAM based synapses integrated into a 3D monolithic technology with two layers of devices in view of neuromorphic architectures
Offer N°: SL-DRT-16-0085
Over the last 50 years, the processor architectures have been based on the von Neumann architecture and the remarkable progress of the Very Large Scale Integration (VLSI) technology allowed to map this computational architecture onto an adequate electronic computing substrate. This combination is not enough today, it is not possible anymore to scale the computational power of classical von Neumann based computing systems by mere brute force approaches.
Impact study and simulation of the a stress field on optical devices in a 3D interposer for advanced silicon photonics.
Offer N°: SL-DRT-16-0430
In the context of short and medium distance transfers of very large amount of numerical data, silicon photonics is an emerging area that provides proven solutions to a major societal challenge. It allows extremely dense data exchanges at low energy cost, perfectly suited to large Datacenters needs.
Fine pitch interconnects, which reliability?
Offer N°: SL-DRT-16-0096
Context/State of the art
The interconnect density required by the next generation 3D IC results in a significant reduction of the dimensions of these interconnects. They consist in metallic pillars (copper / nickel) associated with a solder material (tin / silver).
Scientific and technical obstacles