100 results found

[Thesis]

Cleaning and wet etching processes for metal contact formation on III-V and Ge materials

Offer N°: SL-DRT-14-0122

Start date: 1 Sep 2014

Continued performance scaling of silicon MOS transistors meets immense challenges at sub-10 nm. Therefore, scaling-free technologies are now strongly needed to achieve further improvement of CMOS devices. A number of non-silicon channel materials have been considered for advanced CMOS devices such as SiGe or Ge (PMOS) as well as various III-V materials combinations including InGaAs, GaAs, InAs (NMOS).



[Thesis]

Modular Emission Tomography System based on CdZnTe detectors

Offer N°: SL-DRT-14-0586

Start date: 1 Oct 2014

The Detector laboratory is developing semiconductor radiation detector based systems for medical imaging (radiology, X-CT, SPECT) and safety applications (baggage inspection, nuclear safety). It has been shown that the improvement of signal processing techniques allows to extract for each detected photon several physical parameters: energy, 3D positioning and timestamp.



[Thesis]

New porous materials in the form of nanofibers

Offer N°: SL-DRT-14-0572

Start date: 1 Oct 2014

Discovered in the early 1900's, electrospinning is a long-known polymer processing technique that has recently been rediscovered. It allows for the creation of nanofibers (fibers with a diameter well in the realm of nano dimensions) that can be collected to form a non-woven fabric. The resulting material can be applied to create many products including medical devices, tissue engineering scaffolds, clothing and filtration media.



[Thesis]

Study of assembly technologies for high temperature power components

Offer N°: SL-DRT-14-0568

Start date: 1 Sep 2014

This thesis is integrated in LETI's developments of power transistors, based on gallium nitride material. This wide-bandgap semiconductor allows increased performances of energy converters in terms of efficiency and power density. Compared to silicon components, it permits to work at higher frequencies and temperatures (over 200°C). However, such characteristics imply specific packaging technologies, that are not available in current package technologies developed for silicon transistors.



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