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Offers : 23

Nano-optomechanical silicon accelerometer for high performance applications

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Start date : 1 June 2020

offer n° PsD-DRT-20-0035

Inertial sensors (accelerometers and gyrometers) are at the heart of a large number of consumer-and low-cost applications such as smartphones and tablets, but also higher added value, higher-performance applications such as navigation for autonomous vehicles, aeronautics or space. Silicon microsystems (MEMS) are today a very mature technology and several millions are sold each year. However, they are today unable to address high-performance applications.

LETI has been pioneering the development of optomechanical sensors “on-chip”: light is guided in thin silicon layers in a similar way to photonics techniques. This light interacts with an object in motion such as a mechanical resonator or a seismic mass. This displacement modulates the intensity of the measured light, which allows the determination of the object’s acceleration. This technology was developed in the 2000s in fundamental research, and in particular enabled gravitational wave detectors. LETI is developing this technology on-chip at the nanoscale, with displacement sensitivities several orders of magnitude better than electrical transductions.

First optomechanical accelerometers were designed and fabricated in LETI’s quasi-industrial clean rooms for initial characterization tests. The hired fellow with have to become familiar with these devices, to confirm the first optical results, and then most importantly to assess their performances under acceleration: a test setup will have to be realized for this purpose. She or he will have to provide feedback on the modeling and the design from the measurements in order to ensure the comprehension of all phenomena at play. Finally, the postdoctoral fellow will have to propose new designs aimed at the expected high performances. These devices will be fabricated by the clean room, tested by the fellow and and compared to the expected performance.

Via level hybrid bonding : performance with via size < 500nm

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Start date : 1 April 2020

offer n° PsD-DRT-20-0033

Wafer to wafer hybrid bonding is a mature technology for 3D interconnects with pitch ranging from 1,5 µm to 10 µm. Image sensors or smart displays applications take advantage of hybrid bonding technology compatible with heterogeneous Silicon wafers.

The Post Doc works address the reduction of the actual dimensions of hybrid bonding interconnects with 2 innovations.

In the first one, the proposal is to reduce the number of integration levels. Today 4 integration levels are used for interconnections between 2 wafers with hybrid bonding technology. The interest is to perform wafer to wafer hybrid bonding with only one or 2 levels of integration. For instance the ultimate perspective is to provide hybrid bonding technology with only one via level to electrically connect 2 wafers.

The second one address design constrains relaxations. Indeed actually hybrid bonding technology requires to have very homogeneous metal density in order to have a perfectly flat wafer surface compatible with direct bonding. In the perspective of hybrid bonding at via level, design rule should be extended towards via size < 500nm and low Cu density.

  • Keywords : DCOS, Leti
  • Laboratory : DCOS / Leti
  • CEA code : PsD-DRT-20-0033
  • Contact :

Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing

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Start date : 1 January 2020

offer n° PsD-DRT-20-0029

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).

However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.

The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.

  • Keywords : Electronics and microelectronics - Optoelectronics, DCOS, Leti
  • Laboratory : DCOS / Leti
  • CEA code : PsD-DRT-20-0029
  • Contact :

Design of innovative time-domain microphone readout using Injection Locked Oscillators

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Start date : 1 January 2020

offer n° PsD-DRT-20-0023

Nowadays, Voice Activity Detection is a hot research topic. This application needs the design of high linearity, high dynamic ( > 100 dBSpl) and low noise (< 25 dBSpl) microphones putting stringent requirement on both the transducer and the readout electonics. State of the art microphone readouts are based on a classical amplifier and sigma delta conversion. They fulfill the needs in term of dynamic and noise but at the expense of a high power consumption (1 mW) not compliant with mobile applications.

CEA-LETI is currently working on an innovative transducer design that fulfills the needs in terms of dynamic and noise. To go along with the transducer development, CEA-LETI is searching for a PostDoc whose mission will be to study an Ultra Low Power architecture of readout circuits working in the time-domain and based on Injection Locked Oscillators. The post doc work will consist in an architecture study and its evaluation in term of expected performances. In a second time an optimized chip should be designed and fabricated. Evaluation of the solution will be made by a thorough measurement of the test chip.

  • Keywords : Electronics and microelectronics - Optoelectronics, DACLE, Leti
  • Laboratory : DACLE / Leti
  • CEA code : PsD-DRT-20-0023
  • Contact :

Towards the development of high-performance piezoelectric nano-composites for innovative applications in energy conversion

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Start date : 6 January 2020

offer n° IMEPLaHC-10172019-CMNE

Postdoctoral subject:
Towards the development of high-performance piezoelectric nano-composites for innovative applications in energy conversion
IMEP-LaHC / MINATEC / Grenoble-France


Nanotechnologies, Nanowires, Piezoelectricity, AFM, Multiphysics simulation, Semiconductor Physics and technology.

Description of the project:
Semiconductor piezoelectric nanowires (NWs) (GaN and ZnO among others) have improved piezoelectric properties compared to thin films and bulk materials, due to their greater flexibility and sensitivity to lower forces. An intrinsic improvement in piezoelectric coefficients has also been identified by recent theoretical and experimental studies [1, 2]. We are interested in the integration of these nanostructures into nanocomposites (formed by NWs embedded in a dielectric matrix). Very recent theoretical studies in our team show that these nanocomposites can feature improved performance compared to thin films [3, 4]. This type of material is therefore very interesting for different innovative applications, especially when integrated into a flexible substrate. In this context we focus mainly on sensor and mechanical energy harvesting applications [5, 6].

The candidate will work in the context of several European projects in collaboration with Italian research institutes and French SMEs among others. He/she will contribute to the technological development to integrate piezoelectric nanowire composites on rigid and flexible substrates, to the electromechanical characterization of manufactured devices using specific characterization benches [7, 8] and to the evaluation of this technology for innovative applications.

Depending on his or her expertise, the candidate will participate in the co-supervision of Master and PhD level students on several activities within the group, including (i) the characterization of nanowires and nanocomposites using AFM (Atomic Force Microscopy) techniques and (ii) the multi-physics simulation of the nanocomposite using commercial FEM simulation software (e. g. COMSOL Multiphysics).

The candidate will acquire expertise in (i) energy conversion using piezoelectric materials, (ii) manufacturing and integrating piezoelectric nanowires into functional devices, (iii) electromechanical characterization of nanowires and associated devices, (iv) the design and simulation of nanocomposites integrating piezoelectric semiconductor nanowires, (v) student supervision.

[1] X. Xu, A. Potié, R. Songmuang, J.W. Lee, T. Baron, B. Salem and L. Montès, Nanotechnology 22 (2011)
[2] H. D. Espinosa, R. A. Bernal, M. Minary‐Jolandan, Adv. Mater. 24 (2012)
[3] R. Tao, G. Ardila, L. Montès, M. Mouis Nano Energy 14 (2015)
[4] R. Tao, M. Mouis, G. Ardila, Adv. Elec. Mat. 4 (2018)
[5] S. Lee, R. Hinchet, Y. Lee, Y. Yang, Z. H. Lin, G. Ardila, et al., Adv. Func. Mater. 24 (2014)
[6] R. Hinchet, S. Lee, G. Ardila, L. Montès, M. Mouis, Z. L. Wang Adv. Funct. Mater. 24 (2014)
[7] R. Tao, M. Parmar, G. Ardila, P. Oliveira, D. Marques, L. Montès, M. Mouis Semicond. Sci. Technol. 32 (2017)
[8] D. Menin, M. Parmar, R. Tao, P. Oliveira, M. Mouis, L. Selmi, G. Ardila IEEE Conf. EUROSOI-ULIS (2018)

More information:
Knowledge and skills required:It is desirable that the candidate has knowledge in one or more of these areas: semiconductor physics, finite element simulation, Atomic Force Microscopy (AFM), clean room techniques and associated characterizations (SEM, etc.).
Location: IMEP-LaHC / Minatec / Grenoble, France
Start of the contract: January/February 2020
Duration of the contract: 1 year, renewable eventually
Advisor: Gustavo ARDILA (

About the laboratory:
IMEP-LAHC is located in the Innovation Center Minatec in Grenoble. It works in close partnership with several national and international laboratories and industrial groups, preindustrial institutes and SMEs. The post-doctoral fellow will work in the Micro-Nano Electronics Components team, in the Integrated Nanostructures & Nanosystems group, and will have access to the laboratory’s technological (clean room) and characterization platforms.

Gustavo ARDILA +33 (0)

  • Keywords : Engineering science, Engineering science, Electronics and microelectronics - Optoelectronics, FMNT, IMEP-LaHc
  • Laboratory : FMNT / IMEP-LaHc
  • CEA code : IMEPLaHC-10172019-CMNE
  • Contact :
More information