83 results found

[Thesis]

Space, time and frequency diversity for accurate range and angle of arrival measurement in UWB

Offer N°: SL-DRT-15-0008

Start date: 1 Oct 2015

The objective of the PhD is to explore the use of a 2-4 antennas subsystem with an Ultra-Wide-Band (UWB) RF front-end to bring angle of arrival estimation. The research aims to analyze by models the impact of the propagation, the antennas and the RF path imperfections on the estimation, to establish performance bounds and to propose architectural solutions and algorithms.



[Thesis]

New FDSOI-based integrated circuit architectures sensitive to light for imaging applications

Offer N°: SL-DRT-15-0130

Start date: 1 Sep 2015

It was recently demonstrated that FDSOI (Fully-Depleted Silicon-On-Insulator) transistors electrical characteristics can be sensitive to light illumination provided a diode is monolithically integrated below the BOX (Buried Oxide). In particular the transistor threshold voltage (VT) is significantly tuned by light illumination with this architecture, potentially enabling highly integrated new functions like light detection for More Than Moore applications.



[Thesis]

Exploration of wiring diagnostics via compressive sensing: Algorithms and ultra-compact Analog-to-Information (A2I) architectures

Offer N°: SL-DRT-15-0162

Start date: 1 Oct 2015

Wired networks are considered as the backbones of complex systems. The increase of the complexity of modern systems has come with the increase of wire lengths. Whatever their application domain, wires can be subject to aggressive environmental conditions which may create defects. These defects can have dramatic consequences and if not detected soon can be the cause of deadly accident.



[Thesis]

Hardware support for interprocess communications in multi-core circuits

Offer N°: SL-DRT-15-0005

Start date: 1 Sep 2015

This study aims at improving the performances of synchronization primitives (barriers, distributed mutexes, etc.) in multicore integrated circuits, by offering architectural improvements for transport of synchronization messages, and hardware/software accelerators for the most performance-constrained primitives.



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