Thesis, internship, and post-doc opportunities
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[Thesis]
Development of advanced interconnections for power applications and study of their reliability
Offer N°: 13141
To respond to requirements for environmental protection and alternative energies (solar panels, wind energy, electrical vehicles), CEA-LETI is developing power devices based on HEMT GaN technology (High Electron Mobility Transistor on Gallium Nitride semiconductor). On top of these GaN transistors, a metallic network (also called interconnects) is fabricated to bring current and voltage to the source and drain electrodes of the components.
To respond to requirements for environmental protection and alternative energies (solar panels, wind energy, electrical vehicles), CEA-LETI is developing power devices based on HEMT GaN technology (High Electron Mobility Transistor on Gallium Nitride semiconductor). On top of these GaN transistors, a metallic network (also called interconnects) is fabricated to bring current and voltage to the source and drain electrodes of the components. These interconnects must withstand high current (100A), high voltage (600V), and elevated working temperatures (>250°C). Such operating conditions can lead to metallic reliability issues (diffusion, electro-migration…). This work is focused on the development of advanced interconnections for GaN power transistors and the study of their reliability. After an analysis of the specifications required for these interconnects (current density, electrical field, temperature, geometries...), the work will consist of identifying appropriate materials (eg: aluminium, copper…) and technologies to fabricate them. The interconnect structures produced will be characterized by several physico-chemical and electrical methods. Accelerated aging tests will help to study failure mechanisms. Through optimization of the technological process steps, this work will permit the fabrication of efficient and reliable interconnects.
[Thesis]
Advanced Patterning process development for sub 14nm CMOS technology
Offer N°: 13139
For sub 14nm CMOS technology, Optical lithography based Patterning techniques are limited in terms of minimum dimension and minimum pitch. Alternative techniques, such as ebeam lithography, spacer patterning & direct self assembly, are able to overcome the sub 14nm challenges. One of the key points of such patterning techniques is to have innovative plasma etch processes that will enable the integration of these solutions.
For sub 14nm CMOS technology, Optical lithography based Patterning techniques are limited in terms of minimum dimension and minimum pitch. Alternative techniques, such as ebeam lithography, spacer patterning & direct self assembly, are able to overcome the sub 14nm challenges. One of the key points of such patterning techniques is to have innovative plasma etch processes that will enable the integration of these solutions. Plasma etching processes are able to transfer mask dimension into multi layers stack with a good control of the anisotropy & the selectivity towards the used materials.
The goal of this PhD is to study & develop plasma etching processes for alternatives patterning techniques (Ebeam, DSA, Spacer patterning) to reach the sub 14nm dimension for line/space features.
[Thesis]
Spin Hall effect and spin current absorption
Offer N°: 13137
Spintronics is based on the control of spin currents (different flow of spin up and spin down) to carry and manipulate information. Spin currents produces cab also produce spin transfer torques, and can thus manipulate magnetization states using solely electrical currents. Since a few years the race for industrial developments is on, with mature R&D programs on STT-RAM, a spin transfer torque-based MRAM (Samsung, IBM, Hitachi, Crocus Technology...).
Spintronics is based on the control of spin currents (different flow of spin up and spin down) to carry and manipulate information. Spin currents produces cab also produce spin transfer torques, and can thus manipulate magnetization states using solely electrical currents. Since a few years the race for industrial developments is on, with mature R&D programs on STT-RAM, a spin transfer torque-based MRAM (Samsung, IBM, Hitachi, Crocus Technology...). In a more long term vision the nowadays charge-based information technology could shift toward a spin-based technology, where the spin state would carry the information in a non-magnetic material and spin dependent effects being used to manipulate it. In this context, the project focus on the manipulation of spin currents using recently discovered SO effects, which could lead to new device geometries and concepts with improved working efficiencies and functions.
[Thesis]
Error correction exploiting the properties of emerging digital memories
Offer N°: 13135
Storage memory is one of the major components of modern electronic systems (smart phone, digital camera …). Besides being non-volatile, an ideal storage memory must be fast, dense, power frugal and cheap. Several new non-volatile memories are currently developed (M-RAM, PC-RAM, CB-RAM, Ox-RAM). For some of them, electrical parameters (charge, resistance) used to encode the binary or multi-valued information in storage cells are distributed over a continuous range.
Storage memory is one of the major components of modern electronic systems (smart phone, digital camera …). Besides being non-volatile, an ideal storage memory must be fast, dense, power frugal and cheap. Several new non-volatile memories are currently developed (M-RAM, PC-RAM, CB-RAM, Ox-RAM). For some of them, electrical parameters (charge, resistance) used to encode the binary or multi-valued information in storage cells are distributed over a continuous range. This property may degrade memory reliability and yield due to the inherent variability of memories with high integration densities. On the other hand, the mentioned property could provide new opportunities to provide error detection and correction.
The goal of this thesis is to propose and develop new solutions to improve the yield and reliability of emerging memories. These solutions may rely on new types of algebraic error correcting codes (ECCs) or on new decoding approaches of classical algebraic ECCs which will allow to beneficiate from the special properties of the emerging memories in order to increase the error correction power without affecting the check-bit number (without increasing the storage overhead) and/or improve the error correction speed.
The PhD student will perform his research and development activities within a research group of CEA LIST which is very engaged in the field of integrated circuit reliability and emerging memory technologies. This work can make the object of projects developed in cooperation with industrial and academic partners.
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