Thesis, internship, and post-doc opportunities
144 results found
[Thesis]
New graph partitioning models for tasks assignment and routing on massively parallel architectures
Offer N°: 19729
The emergence, in recent years, of the so-called many-core processor architectures, that is microprocessors integrating hundreds if not thousands cores on a single chip, has created a new field of applications for graph partitioning problems. Indeed, graph partitioning issues are central when one needs to map a network of tasks on such an architecture.
The emergence, in recent years, of the so-called many-core processor architectures, that is microprocessors integrating hundreds if not thousands cores on a single chip, has created a new field of applications for graph partitioning problems. Indeed, graph partitioning issues are central when one needs to map a network of tasks on such an architecture. Still, the first models which have been studied only coarsely reflect the true complexity of the underlying architectures and new, more complete, models are required.
In this context, a first objective of the proposed PhD thesis will be to focus on defining new models which will then induce new variants of the graph partitioning problem. A second objective will be to focus on studying their mathematical structure so as to propose, and experimentally validate, practically relevant resolution algorithms.
[Thesis]
Line dimension variability reduction during interconnect etching for 14nm technological node
Offer N°: 19731
For the 14nm FDSOI technology, the combination lithography and etching steps used in the realization of integrated circuit become more and more complex. The requirement is to obtain small dimension features (few 10 nanometers) on silicon wafers to get high performance devices. Today, one of the most critical steps to achieve this requirement is the interconnection realization. Indeed the difficulty is to achieve 32nm copper line.
For the 14nm FDSOI technology, the combination lithography and etching steps used in the realization of integrated circuit become more and more complex. The requirement is to obtain small dimension features (few 10 nanometers) on silicon wafers to get high performance devices. Today, one of the most critical steps to achieve this requirement is the interconnection realization. Indeed the difficulty is to achieve 32nm copper line. This dimension has to be perfectly controlled within the die thru the 300mm silicon wafer. But the lithography and etching steps used for interconnect realization lead to dimension control variability. The goal of this thesis is to understand this variability as a function of the different etching chemistry and materials used in the interconnection realization.
The etching process will be developed at ST Microelectronics on new etch tools then characterized on the CEA-LETI site thru a close collaboration between researcher from CNRS-LTM and CEA-LETI. The understanding of plasma surface interaction function of the etch chemistry/materials will be studied on CEA-LETI etch tools using complementary usefull characterization techniques like XPS, infrared spectroscopy, TEM-EELS…
[Thesis]
Organized nanostructures studied by small angle X-ray scattering
Offer N°: 19719
The study of nano-objects requires the development of dedicated techniques in order to characterize their form, their size and their spatial organization. Complementary to other microscopy techniques (TEM, SEM, AFM, STM) - the Small Angle X-ray Scattering at Grazing Incidence (GISAXS) known in this context a boom.
The study of nano-objects requires the development of dedicated techniques in order to characterize their form, their size and their spatial organization. Complementary to other microscopy techniques (TEM, SEM, AFM, STM) - the Small Angle X-ray Scattering at Grazing Incidence (GISAXS) known in this context a boom. It makes it possible to obtain a non-destructive, statistical information averaged over the whole sample and allows a meaningful comparison with the physical properties observed at the macroscopic scale. In addition, through modulation of the X-ray penetration into the material with the grazing angle, islands deposited on a substrate as well as nanostructures buried at different depths can be characterized. Finally, the technique can be performed in situ and in real time under many environments. Within the LETI, applications of this technique are numerous: lithography, advanced interconnections ... The thesis will focus on the development of GISAXS in the case of well-organized nanostructures. This will include the developments of tools of modeling/simulation of the of X-ray diffusion by these structures. These developments will be applied to the “state of the art” grapho-epitaxial copolymers developed in LETI and which have already been studied in-situ by GISAXS at the ESRF (European Synchrotron Radiation Facility - Grenoble). The objective is to better understand the ordering of these materials. Finally, the applicants could combine the GISAXS results with other characterization tools (CD-AFM, CD-SEM ...) already performed on these copolymers. Experiments will take place both at the ESRF and in the LETI laboratory which will benefit from a new SAXS/GISAXS instrument in end 2013. This topic is the opportunity to work in the environment of a European synchrotron and the most advanced materials developed MINATEC for micro-nano technologies
[Thesis]
PowerAmplifier-Antenna co-design for high efficiency miniature RF transmitter modules
Offer N°: 19723
CEA-LETI currently leads research activities towards integration of RF systems on chip to propose compact and high efficiency solutions for future wireless applications. In this context, new integration schemes have to be investigated and objectives of the thesis will be to study new architectures and circuits in order to propose miniature RF transmitter modules with low loss.
CEA-LETI currently leads research activities towards integration of RF systems on chip to propose compact and high efficiency solutions for future wireless applications. In this context, new integration schemes have to be investigated and objectives of the thesis will be to study new architectures and circuits in order to propose miniature RF transmitter modules with low loss. The proposed solutions will have to take benefit of a PA-Antenna co-design approach and demonstrators in the 0.5–5 GHz frequency range with high efficiency watt-level characteristics will be developed and integrated in SOI CMOS technology to validate the proposed solutions.
The candidate should be highly motivated and self-working, and be familiar with analog and RF CMOS integrated circuits. He should also be familiar with CAD tools such as CADENCE and ADS. In addition, antenna design notions will be highly appreciated.
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