Thesis, internship, and post-doc opportunities
New graph partitioning models for tasks assignment and routing on massively parallel architectures
Offer N°: 19729
The emergence, in recent years, of the so-called many-core processor architectures, that is microprocessors integrating hundreds if not thousands cores on a single chip, has created a new field of applications for graph partitioning problems. Indeed, graph partitioning issues are central when one needs to map a network of tasks on such an architecture.
Line dimension variability reduction during interconnect etching for 14nm technological node
Offer N°: 19731
For the 14nm FDSOI technology, the combination lithography and etching steps used in the realization of integrated circuit become more and more complex. The requirement is to obtain small dimension features (few 10 nanometers) on silicon wafers to get high performance devices. Today, one of the most critical steps to achieve this requirement is the interconnection realization. Indeed the difficulty is to achieve 32nm copper line.
Organized nanostructures studied by small angle X-ray scattering
Offer N°: 19719
The study of nano-objects requires the development of dedicated techniques in order to characterize their form, their size and their spatial organization. Complementary to other microscopy techniques (TEM, SEM, AFM, STM) - the Small Angle X-ray Scattering at Grazing Incidence (GISAXS) known in this context a boom.
PowerAmplifier-Antenna co-design for high efficiency miniature RF transmitter modules
Offer N°: 19723
CEA-LETI currently leads research activities towards integration of RF systems on chip to propose compact and high efficiency solutions for future wireless applications. In this context, new integration schemes have to be investigated and objectives of the thesis will be to study new architectures and circuits in order to propose miniature RF transmitter modules with low loss.