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Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing

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Start date : 01/01/2020

offer n° PsD-DRT-20-0029

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).

However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.

The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.

  • Keywords : New computing paradigms, circuits and technologies, incl. quantum, DCOS, Leti
  • Laboratory : DCOS / Leti
  • CEA code : PsD-DRT-20-0029
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