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Digital circuit design for In-Memory Computing in advanced Resistive-RAM NVM technology

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Start date : 01/02/2021

offer n° PsD-DRT-21-0049

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).

CEA-Leti launched a project on this topic, leveraging three key enabling technologies, under development at CEA-Leti: non-volatile resistive memory (RRAM), new energy-efficient nanowire transistors and 3D-monolithic integration [ArXiv 2012.00061]. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems.

  • Keywords : Technological challenges, Artificial intelligence & Data intelligence, New computing paradigms, circuits and technologies, incl. quantum, DCOS, Leti
  • Laboratory : DCOS / Leti
  • CEA code : PsD-DRT-21-0049
  • Contact : francois.andrieu@cea.fr
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