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Binary Neural Networks based on CMOS/RRAM hybrid architecture

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Start date : 1 August 2018

offer n° SL-DRT-18-0498

Recent research has theoretically demonstrated that it is possible to implement binary-weight CNNs with only small accuracy losses on several well known benchmarks [M. Rastegari et al. arXiv:1603.05279, M. Courbariaux et al., arXiv:1602.02830]. Binary weights (i.e., weights which are constrained to only two possible values, e.g. 0 or 1) can be directly mapped into digital RRAM arrays. The RRAM arrays can be employed as both storage and computation element with minimized leakage power due to its non-volatility.

The man objective of this thesis is the study of digital RRAM arrays for the hardware implementation of CNNs. Both, hybrid CMOS/RRAM (1T1R arrays) and back-end selector/RRAM (1S1R crossbar) technologies will be investigated to implement the hardware convolution kernels. The bitwise convolution and pooling function have to be investigated using both 1T1R and 1S1R architectures. For the 1S1R architectures different reading schemes will be investigated, based on the current level and current switch detection respectively.

  • Keywords : Engineering science, Electronics and microelectronics - Optoelectronics, DCOS, Leti
  • Laboratory : DCOS / Leti
  • CEA code : SL-DRT-18-0498
  • Contact : elisa.vianello@cea.fr
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