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Optimization of countermeasure insertion for the safety of Integrated Circuits.

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Start date : 1 October 2019

offer n° SL-DRT-19-0681

Hardware Trojans (HTs) are malicious blocks inserted into Systems on Chip (SoC) by untrusted parties in the IC design/manufacturing flow. They have been identified as a realistic threat, among others to the car safety and military. HTs aim to change SoCs’ behavior, ranging from denial of service, decreased reliability, to confidential information leakage. Such attacks lead to multi-billions dollars loss per year for the semiconductor industry. Countermeasures against HTs exist, divided into two categories: detection and prevention. Ten years of research have shown that detection is a very challenging task, knowing the stealthy nature of the threat and the multiple possible forms of HTs. Prevention consists in modifying the design flow to take into account security issues. Despite its potential cost, it represents a more effective way to overcome HT insertion. So-called Design-for-Hardware-Trust (DfHT) methods exist, with various goals and impacts on performance. The MOOSIC project proposes a framework dedicated to security that can be integrated into the conventional IC design flow. The goal is to take into account, as early in the design phase, both countermeasures against HTs and performance, to ensure that the SoC behavior is guaranteed despite untrusted IPs vendors or foundry. Towards this objective, the project envisions to establish and evaluate security properties and then integrate them during synthesis with multi-objective optimization techniques, which will be built on a mathematical modeling of the problem that takes into account both the performance and the HTs‘effects. It is indeed necessary to find a good compromise between the level of security sought after and performance.

The candidate will have to propose a complete mathematical model of the problem that supports all the constraints and objectives (security, area, frequency, consumption). He will then have to develop optimization algorithms to effectively solve the problem of insertion of countermeasures on conventional criteria (time, area, consumption). Finally, a validation of the methodology on simple first examples is envisaged as well as some test on industrial use cases improvement with some improvement if necessary. The thesis will take place at the CEA LIST LCE and will be led by the LIP6 / Sorbonne University in Paris.

  • Keywords : Engineering science, Computer science and software, DACLE, Leti
  • Laboratory : DACLE / Leti
  • CEA code : SL-DRT-19-0681
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