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Design for reliability for digital circuits

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Start date : 1 March 2018

offer n° PsD-DRT-18-0010

Flash memories are a key enabler for high-temperature applications such as data acquisition and engine control in aerospace, automotive and drilling industries. Unfortunately, the retention time of flash memories is very sensitive to high temperatures. Even at relatively moderated temperatures, flash memories may be affected by retention-related problems especially if they are set to store more than one bit per cell. This impact can be mitigated by periodically refreshing the stored data. The problem is that, in the presence of a variable operating temperature that could be due to variable environmental and workload conditions, a fixed data-refresh frequency may become disproportionately large with a subsequent impact on response time and cycling endurance.

The first objective of this project is to implement a data-refresh method based on a specially designed counter that is able to (a) track the evolution of the temperature and its impact on the data retention time of Flash memory blocks, (b) trigger warnings against potential retention time hazards and (c) provide timestamps.

The second objective is to find the distribution law that gives the evolution of the number of data retention errors in time. The goal is to implement a methodology able to infer the remaining retention time of flash memory pages based on their data retention age, i.e., the elapsed time since data was stored, and the number of retention and non-retention errors.

The publication of the scientific results in high-ranked conferences and journals is major project objective.

  • Keywords : Engineering science, Electromagnetism - Electrical engineering, Electronics and microelectronics - Optoelectronics, DACLE, Leti
  • Laboratory : DACLE / Leti
  • CEA code : PsD-DRT-18-0010
  • Contact : valentin.gherman@cea.fr
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